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Back-Annotation Timing Data May Contain Overly Conservative Values for the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical Post-lay out Simulation Occurs When NGDAnno Is Called Without a Reference to the NGM File .


Record #1863

Problem Title:
Back-Annotation Timing Data May Contain Overly Conservative Values for
the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical
Post-lay
out Simulation Occurs When NGDAnno Is Called Without a Reference to the NGM
File
.



Problem Description:
Platform: All
Architecture: XC4000E -2 and -3
Design Step: NGDAnno and Post-Layout Timing Simulation
Reference Number: 11562
The back-annotation timing data for input flip-flops and latches with the NODELA
Y attribute may contain PAD-to-IOB-IK-pin setup requirements that are 0.1ns (TTL
 mode) to 1.6ns (CMOS mode) too great. NGDAnno will issue a warning of the follo
wing type whenever it detects that a conservative value is being assigned to an
IOB flip-flop/latch setup field:
WARNING:0 - Negative setup value of -1590 on block
MY_IOB/INBLOCK/IN_LATCH/LATCH, pin IN will be set to zero.
block name is of the form "iob_name/INBLOCK/IN_LATCH/
..." or "iob_name/INBLOCK/INFF/..." The pin name "IN" indicates
that the setup check on the data input pin is the affected cell. Setup times are
 reported in picoseconds.


Solution 1:

Setup violations that occur during timing simulation should be investigated to d
etermine whether they fall within these conservative time-windows. If so, they m
ay safely be ignored. For example, assume that NGDAnno had issued the warning sh
own above. If your simulator reports a setup violation of 900ps at the latch MY_
IOB/INBLOCK/IN_LATCH/LATCH, it may safely be ignored because 900ps is less than
the 1590ps mentioned in the warning.



End of Record #1863