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M1.1.1a NGD2VER Writes Out a Verilog Output File with a `uselib Line Indicating the Location of the Simprim Libraries


Record #1864

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.1.1a NGD2VER Writes Out a Verilog Output File with a `uselib Line
Indicating the Location of the Simprim Libraries



Problem Description:
Keywords: uselib simprim verilog libraries

Urgency: standard

General Description:
NGD2VER vM1.1a default behavior is to write out a Verilog output File with a
`uselib directive pointing to the location of the Simprim Libraries.

`uselib is a Cadence Verilog-XL-specific directive that is not recognized
by non-Cadence Verilog simulators. This default behavior of NGD2VER will
be changed to write out "`uselib" only if the -ul option is specified.



Platform(s): All
Architecture(s): All
Design Step(s): NGD2VER
Reference Number: 13066


Solution 1:

The presence of the `uselib line may cause problems for other
third party Verilog simulators.  For example, the Mentor
QuickHDL Verilog simulator cannot determine the path for the
libraries based on the `uselib directive, and issues an error
indicating that the directory cannot be found. You can still
simulate the design, however, by specifying the required library on your command
 line when you invoke the simulator.

This problem will be fixed in NGD2VER m1.2.x by requiring that
a new -ul option be specified for this line to be written out.

Workaround:
Manually deleting this line from the .v file will get rid of this error.



End of Record #1864