Answers Database
M1.5 TRCE: IOB register to PAD paths (and vice-versa) are not reported or controlled
Record #1867
Product Family: Software
Product Line: FPGA Implementation
Problem Title:
M1.5 TRCE: IOB register to PAD paths (and vice-versa) are not reported
or controlled
Problem Description:
Keywords: TRACE, TRCE, IFD, IFF, ILD, OFD, clock2pad, pad2setup
Reference Number: 14018
TRACE does not report timing-related data associated with PADS
and FLIP FLOPS when the flip flop is contained (implemented) in an IOB component
. This occurs for both for explicit instantiations of IFFs and OFFs and for flip
flops packed into an IOB during the mapping process (controllable with the -pr
switch).
Solution 1:
Workaround: The timing between the PAD and FF is fixed (and
known) for each device, but is not reported by TRCE. There is no known workaroun
d for having TRCE report these numbers, but the numbers
reported in the Data Book Guaranteed Input and Output Parameters
are considered valid.
End of Record #1867
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |