Answers Database

VERILOG-XL board level simulation SDFA Error: Type of INSTANCE xxxx doesnot match CELLTYPE <cell_name> in Verilog-XL.


Record #1895

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL board level simulation SDFA Error: Type of INSTANCE xxxx
doesnot match CELLTYPE <cell_name> in Verilog-XL.



Problem Description:
Keywords: verilog sdf annotator match cell instance uselib board

Urgency:  standard

General Description:
The SDF Annotator issues an error message similar to the following:

 Reading SDF file and back-annotating timing data...

15:  Error:  Type of INSTANCE design.lca_ms._XSYMDFFCLR38 (buff$inst2_2$4)
does not match CELLTYPE buff

This may be seen when doing a board level simulation incorporating multiple
Verilog netlists using "`uselib" directives that reference libraries with
similar cell names. When simulations are run on the individual Verilog
netlists by themselves, SDF Annotate operates properly, but doing a complete
board level simulation with multiple netlists and their associated SDF files
causes this error to appear.

In the multiple Verilog netlist situation (such as in a board level
simulation), the "`uselib" compiler directive changes the duplicate
module or primitive names to make them unique.	The side effect of this
is that once the module and primitve names have been changed, the SDF
Annotator is no longer able to match up the original instance types to the
cell types in the netlist.



Solution 1:

The workaround is to invoke Verilog-XL with the command-line option, +sdf_nochec
k_celltype.  Basically this option tells the SDF Annotator
_not_ to check the CELLTYPE against the type of cell instance
specified by the INSTANCE keyword.

The +sdf_nocheck_celltype option is documented in the 9604 release of Openbook
in section 22 of the Verilog-XL Reference Guide.




End of Record #1895