Answers Database

M1 and MTI: How to compile the HDL simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)


Record #1923

Product Family:  Software

Product Line:  Model Technology

Problem Title:
M1 and MTI: How to compile the HDL simprim, LogiBLOX, Unisim, and
Coregen libraries (VHDL and Verilog)



Problem Description:
Keywords: vcom, vlog, v-system, model technology, simulation,
	  simprims, LogiBLOX, Unisims, VHDL, Verilog, VITAL,
	  modelsim, vsim, compile, library, xul

Urgency: Standard

General Description:

To perform timing or post-synthesis functional HDL simulation in M1,
the Verilog and/or VHDL (VITAL) simprim models must be compiled for
use in the Model Technology simulator.	If instantiated LogiBLOX and/or
Unified library components are to be behaviorally simulated, the
LogiBLOX and/or Unisim libraries must be compiled, as well.

This solution record is written for the Modelsim versions
(5.1x for workstation or 4.7x for PC).	This solution is
applicable for earlier versions of the simulator if the word
MODELSIM is replaced with V-SYSTEM.

For more information on the Modelsim-Xilinx VHDL flow, please
refer to the Model Technology Application Note, "HDL Simulation
FPGA Design Methodology" at
http://www.model.com/pdf/100exemxilinx.pdf


Solution 1:

M1 contains three types of HDL simulation libraries and Coregen
conatins one:

   simprim  - Library of generic simulation primitives
   LogiBLOX - Library of LogiBLOX simulation models (VHDL only)
   unisim   - Library of Unified component simulation models (A1.4+)
   xul	    - Coregen VHDL Library containing some arithmetic functions


The instructions that follow reference the following variables:

   VERILOG_DESTN - Location for compiled Verilog libraries
		   Example setting: $MODEL_TECH/xilinx/verilog

   VHDL_DESTN	 - Location for compiled VHDL libraries
		   Example setting: $MODEL_TECH/xilinx/vhdl

If you want logical library names to be available for all designs, set your
MODELSIM environment variable to the location of your master .ini file,
e.g.:

   setenv MODELSIM $MODEL_TECH/Xilinx/modelsim.ini

If MODELSIM is not set when vmap is run, the logical library mapping is done
locally, and therefore all vmap commands would have to be run for each new
HDL design.

For Verilog users, the compilation commands that need to be executed are:

   SIMPRIM
   -------
   vlib $VERILOG_DESTN/simprim
   vmap simprim $VERILOG_DESTN/simprim
   vlog -work simprim $XILINX/verilog/data/*.vmd

   LogiBLOX
   --------
   (none required)

   UNISIM (Versions A1.4 and later)
   --------------------------------
   vlib $VERILOG_DESTN/uni3000
   vmap uni3000 $VERILOG_DESTN/uni3000
   vlog -work uni3000 $XILINX/verilog/src/UNI3000/*.v

   vlib $VERILOG_DESTN/uni4000e   # Not included in compile script
   vmap uni4000e $VERILOG_DESTN/uni4000e
   vlog -work uni4000e $XILINX/verilog/src/UNI4000E/*.v

   vlib $VERILOG_DESTN/uni4000x
   vmap uni4000x $VERILOG_DESTN/uni4000x
   vlog -work uni4000x $XILINX/verilog/src/UNI4000X/*.v

   vlib $VERILOG_DESTN/uni5200
   vmap uni5200 $VERILOG_DESTN/uni5200
   vlog -work uni5200 $XILINX/verilog/src/UNI5200/*.v

   vlib $VERILOG_DESTN/uni9000	  # Not included in compile script
   vmap uni9000 $VERILOG_DESTN/uni9000
   vlog -work uni9000 $XILINX/verilog/src/UNI9000/*.v


   Note:  To refernce these libraries during Verilog simulation,
	  the -L switch must be specified during VSIM execution
	  specifying library name given for the VMAP command.

   Example for Verilog timing simulation:

   vlog testbench.v time_sim.v
   vsim -L simprim testbench_module_name


For VHDL users, the commands are:

   SIMPRIM
   -------
   vlib $VHDL_DESTN/simprim
   vmap simprim $VHDL_DESTN/simprim
   vcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
   vcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
   vcom -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd

   LogiBLOX
   --------
   vlib $VHDL_DESTN/logiblox
   vmap logiblox $VHDL_DESTN/logiblox
   vcom -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
   vcom -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
   vcom -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd

   UNISIM (Versions A1.4 and later)
   --------------------------------
   vlib $VHDL_DESTN/unisim
   vmap unisim $VHDL_DESTN/unisim
   vcom -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
   vcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
   vcom -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
   vcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

   vlib $VHDL_DESTN/unisim_5k
   vmap unisim_5k $VHDL_DESTN/unisim_5k
   vcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
   vcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
   vcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
   vcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
   vcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd

   Coregen (Coregen must be installed seperatly from M1)
   -----------------------------------------------------
   vlib $VHDL_DESTN/xul
   vmap xul $VHDL_DESTN/xul
   vcom -work xul $COREGEN/ip/xilinx/xul/ul_utils.vhd

   Note: $COREGEN refers to the location wheer Coregen was
	 installed on the system



End of Record #1923