Answers Database

XNF specification: Naming Conventions for nets, buses, components and pins


Record #1964

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XNF specification: Naming Conventions for nets, buses, components and
pins



Problem Description:
Keywords: naming, convention, xnf, specification, nets, buses,
	  component, pins, labels

Urgency: Standard

General Description: A specific naming convention needs to be
followed for the naming of nets, buses, components and pins in
a design in order to follow the xnf specification.  While
this list covers most of them, please refer to your design
entry tool's user guide for additional conventions that may
apply specifically to the design entry tool/simulator that you
are using.


Solution 1:

FPGA names for nets, buses, components, and pins must follow
these conventions:

- Only A-Z, a-z, 0-9, _, and - are allowed in user-defined
  names.  No other characters should be included in names.

- No spaces are allowed.

- Names must contain at least one non-numeric character.

- Names cannot be more than 1024 characters long.

- Reserved words such as : CLB, IOB, CCLK, DP, GND, VCC, RT,
  PWRDN, RST, TDO, BSCAN, M0, M1, M2, STARTUP as well as
  package pin names (P1, P2, A4, B5, etc.), CLB names (AA, AB,
  R1C3, etc) or Xilinx primative names (FD, PULLUP, BUF, etc)
  should not be used.

-  Square brackets, [], are generally used for bus notation
   and should not be used unless defining the bounds of a bus.



End of Record #1964