Answers Database

CONCEPT2XIL/LOGIBLOX: "Unknown child port declaration" / "Architecture not found errors"


Record #2042

Product Family:  Software

Product Line:  Cadence

Problem Title:
CONCEPT2XIL/LOGIBLOX: "Unknown child port declaration" / "Architecture
not found errors"



Problem Description:
Keywords:  expand hierarchy child port decl architecture
logiblox

Urgency: standard

General Description:

CONCEPT2XIL issues the error:

<output>
Expanding design hierarchy ...
Unknown child port decl:   o
Occurrence andblox_0 -> top_lib.X_AND2.hdl: Error! Architecture not found in you
r design library.
</output>

OR

<output>
Expanding design hierarchy ...
Occurrence AND1BINLD0 -> topcounter_lib.X_AND2.hdl:
Error! Architecture not found in your design library
</output>

You may see one of the two errors above if you are executing
CONCEPT2XIL on a design that contains a LogiBLOX module or
other non-schematic block within it, for which you have
generated a symbol using GENVIEW. (LogiBLOX must be run
standalone if you are using Cadence Concept in M1)

The error is seen if the verilog.v file corresponding
to the non-schematic block is missing the following
parameter definition in the module declaration:

<input>
   parameter cds_action = "ignore";
</input>

(Reference #12498)


Solution 1:

The solution is to add the cds_action="ignore" parameter
to the offending non-schematic block verilog.v file.

<input>
  parameter cds_action="ignore";
</input>

The verilog.v file is usually located in the logic view
(subdirectory) for the block.  The parameter needs to be
declared somewhere at the beginning of the Verilog module
declaration for the block.  Its function is to signal to the
CONCEPT2XIL netlister that it should not try to find another
level of hierarchy under the non-schematic block containing
this parameter.



End of Record #2042