Answers Database

Problem with pin mismatch, macro in Workview Office, xnf from Synplicityor FPGA Express


Record #2076

Product Family:  Software

Product Line:  ViewLogic

Problem Title:
Problem with pin mismatch, macro in Workview Office, xnf from
Synplicityor FPGA Express



Problem Description:
Keywords: net, bus, macro, xnf, Viewlogic, Synplicity, Express

Urgency: Standard

Viewlogic writes out busses in xnf files with square brackets [] and both
Simplify 3.0 and FPGA Express 1.2/2.0 (and undoubtedly many others) write out
XNF files with angle brackets <>.  Then viewing the nets on these buses,
Synplicity/Express bus nets will have angle brackets, but Viewlogic bus nets
will have no brackets at all.

This becomes a problem when you create a macro in Viewlogic that references
an .xnf file from Simplicity or Express.  The convention mismatch will not
allow the sub-hierarchy to be merged by ngdbuild.


Solution 1:

The workaround is to manually change the bus names in the .XNF file(s).
Globally remove the angle bracket instances.

Therefore:

BUS<3>

becomes

BUS3



End of Record #2076