Answers Database

M1/FPGA Compiler: Sometimes set_false_path/set_max_delay not translated by write_script


Record #2089

Product Family:  Software

Product Line:  Synopsys

Problem Title:
M1/FPGA Compiler: Sometimes set_false_path/set_max_delay not translated
by write_script



Problem Description:
keywords:FPGA Compiler,3.5a,3.4b, 1997.01 ,write_script,dc2ncf,set_max_delay,set
_false_path

urgency: hot

general description:

In FPGA Compiler v3.4b, v3.5a, and v1997.01 after the replace_fpga command is ru
n, the set_max_delay and set_false_path constraints executed before 'compile' ar
e removed from the Synopsys shell environment.	When write_script is executed af
ter replace_fpga,
any set_false_path or set_max_delay constraints executed before replace_fpga wil
l be removed from the Synopsys environment; write_script translates all timing c
onstraints set by the user. But, replace_fpga removes set_max_delay and set_fals
e_path
constraints, so the .dc file created by write_script
will be missing constraints.


Solution 1:

The workaround is to reapply the set_max_delay
and set_false_path constraints, after the replace_fpga
command, and just before running the write_script command.

Depnding on the compile strategy used, just reapplying
the set_max_delay and set_false_path constraints again
may not produce timespecs, since the ports, clocks, and
cells used in the original set_max_delay and
set_false_path constraints may not exist due to
optimization by compile.  Reapplied set_max_delay
and set_false_path constraints will be translated to
a valid .ncf file, if the names used in the <from> and
<to> lists are cell/top-level port names which are listed by
the report_port, all_clocks, all_registers, all inputs, and all_outputs
 commands, which are executed after the ungroup -all -flatten command.

report_port, all_clocks, all_registers, all_inputs, and all_outputs are commands

in FPGA Compiler v3.4b, v3.5a, and v1997.01  With the
current_design set to the top level of hierarchy, use
report_port to get a list of all top-level ports;
'top-level ports' in FPGA Compiler are equivalent to
PADS in the FROM:TO TIMESPEC nomenclature.  With
current_design set to the top-level of hierarhcy, the
all_clocks command will list all clocks that have
been defined by create_clock.  all_registers lists
all registers, latches, and instatiated
synchronous/dual-port RAM's.  all_registers list
all the registers, latches, and instantiated
synchornous/dual-port RAM's with their full
hierarchial names.  With the current_design set to the top-level,
all_inputs lists all top-level ports with a direction of in or inout.
With the current_design set to the top-level, all_outputs lists
all top-level ports with a direction of out.




Solution 2:

Example of Verilog runscript with reapplication of
set_max_delay and set_false_path constraints:

read -f verilog file1.v
read -f verilog file2.v
.
.
read -f verilog filen.v

set_port_is_pad "*"
insert_pads

/*Set Timing Constrinats */
create_clock...
set_max_delay
set_false_path

compile
replace_fpga

ungroup -all -flatten
/*Reapply Timing Constraints*/

all_clocks
all_registers
all_inputs
all_outputs
set_max_delay...
set_false_path...
write_script > "top.dc"
sh dc2ncf "top.dc"
exit



Solution 3:

Example of VHDL runscript with reapplication of
set_max_delay and set_false_path constraints:

analyze -f vhdl file1.vhd
analyze -f vhdl file2.vhd
.
.
elaborate TOPLVLENTITY

set_port_is_pad "*"
insert_pads

/*Set Timing Constrinats */
create_clock...
set_max_delay...
set_false_path...
set_input_delay...
set_output_delay...

compile
replace_fpga

ungroup -all -flatten
/*Reapply Timing Constraints*/
report_port
all_clocks
all_registers
all_inputs
all_outputs
set_max_delay...
set_false_path...
write_script > "top.dc"
sh dc2ncf "top.dc"
exit



End of Record #2089