Answers Database

PRE-M1.0 CADENCE CONCEPT: Invisible property SIG_NAME="GSR \G": Illegal HDL name: illegal character after signal or port


Record #2103

Product Family:  Software

Product Line:  Cadence

Problem Title:
PRE-M1.0 CADENCE CONCEPT: Invisible property SIG_NAME="GSR \G": Illegal
HDL name: illegal character after signal or port



Problem Description:
Keywords: invisible property signame sig_name gsr gts
illegal character hdl direct global

Urgency: standard

General Description:

ERROR: "Invisible property SIG_NAME="GSR \G": Illegal HDL
name: illegal character after signal or port

In versions of Concept supporting HDL Direct, saving a logic
drawing with the "check_net_names_hdl_ok" variable enabled may
result in the following errors:

on FLIP-FLOPs:

   '"Invisible property SIG_NAME="GSR \G": Illegal HDL name:
    illegal character after signal or port name"'

On OBUFTs:

the error is similar, but refers to to GTS:

   'ERROR: "Invisible property SIG_NAME="GTS \G":
    Illegal HDL name: illegal character after
    signal or port name.'


This error is generally seen on designs or libraries
which have been entered using the SCALD design methodology.
In the SCALD methodology, global signals are flagged as such
by appending a "\G" suffix to the signal name.	However,
in HDL Direct methodology, Verilog and VHDL naming
conventions must be respected, and "\" is not a legal
character.

The correct way to designate a signal as a global signal
in HDL Direct methodology is to prefix it with a forward
slash ("/").



Solution 1:

Change all "GSR\G" signame properties to  "/GSR", and all
"GTS\G" properties to "/GTS".



End of Record #2103