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Foundation HDL Editor: ABEL state diagram template gives grounded outputs.


Record #2110

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation HDL Editor: ABEL state diagram template gives grounded
outputs.



Problem Description:
Keywords: foundation abel hdl state machine
Urgency:  Standard

General Description:
Selecting the state-machine language template (Tools ->
Language Assistant -> Templates -> Language Templates ->
definition constructions -> state diagram) and using the
template in an ABEL design results in constantly low outputs
during simulation.


Solution 1:

The first defined state contains an error, and the
state_diagram section of the template is incomplete.

In the state_diagram section, the description of S0 is
incorrect as the machine remains in S0 not only if Clr=1 but
also if Dir=1. It should progress to S1 if Dir=1.

By default, all flip-flop outputs will initially be low. This
is defined as state S15 in the declarations section. However,
S15 is not listed in the state_diagram section and therefore
the flip-flops remain in their current state with their
outputs low.

After including the template into your ABEL code, change it
to the following to achieve the expected results.

 Module statmach
 Title 'Up/Down Counter with Synchronous Clear'

 Declarations

	Clk	pin;
	Clr,Dir	pin;
	Q3..Q0	pin istype 'reg';


	" Counter States
	S0 = ^b1111; S4 = ^b1011; S8 = ^b0111; S12= ^b0011;
	S1 = ^b1110; S5 = ^b1010; S9 = ^b0110; S13= ^b0010;
	S2 = ^b1101; S6 = ^b1001; S10= ^b0101; S14= ^b0001;
	S3 = ^b1100; S7 = ^b1000; S11= ^b0100; S15= ^b0000;

	CNT = [Q3,Q2,Q1,Q0];

 Equations

	CNT.CLK = Clk;

 State_diagram [Q3,Q2,Q1,Q0]

  State S0:	if Clr then S0
	    else if Dir then S1
	    else S9;
  State S1:	if Clr then S0
	    else if Dir then S2
	    else S0;
  State S2:	if Clr then S0
	    else if Dir then S3
	    else S1;
  State S3:	if Clr then S0
	    else if Dir then S4
	    else S2;
  State S4:	if Clr then S0
	    else if Dir then S5
	    else S3;

  State S5:	if Clr then S0
	    else if Dir then S6
	    else S4;
  State S6:	if Clr then S0
	    else if Dir then S7
	    else S5;
  State S7:	if Clr then S0
	    else if Dir then S8
	    else S6;
  State S8:	if Clr then S0
	    else if Dir then S9
	    else S7;
  State S9:	if Clr then S0
	    else if Dir then S10
	    else S8;
 State S10:	if Clr then S0
	    else if Dir then S11
	    else S8;
  State S11:	if Clr then S0
	    else if Dir then S12
	    else S10;
  State S12:	if Clr then S0
	    else if Dir then S13
	    else S11;
  State S13:	if Clr then S0
	    else if Dir then S14
	    else S12;
  State S14:	if Clr then S0
	    else if Dir then S15
	    else S13;
  State S15:	if Clr then S0
	    else if Dir then S0
	    else S13;

  End statmach



End of Record #2110