Answers Database

COREGEN: SYNOPSYS VHDL FLOW


Record #2116

Product Family:  Software

Product Line:  Coregen

Problem Title:
COREGEN: SYNOPSYS VHDL FLOW


Problem Description:
Keywords: DSP, Coregen, Core Generator.

Urgency: Standard

How to use the Core Generator in a SYNOPSYS VHDL Flow.


Solution 1:

There is a step-by-step tutorial describing this procedure
in the CoreGen User Guide.  A less detailed procedure
is listed below:

1)  Create a  working directory from which you will start
Coregen:
	  Example: c:\proj\myproj


2) Start Coregen from the Windows Start menu by selecting
"Coregen" from the Xilinx Core Generator shortcut directory.

3) Set the output format options by clicking on
Options->Output format and select:

   - VHDL Instantiation Template
   - XNF Implementation Netlist
   - VHDL Behavioral Simulation Model


4)  Check that all your paths are set properly by looking at
the menu Options->System options.  Only the ProjectPath
setting should require modification by the user.  Modify
this path to point to c:\proj\myproj.

5)  Select the module that you want to generate by clicking on
the file icon corresponding to the module.  (Note
that the generation of a core cannot be activated by clicking
on the module *name* in this release.)

6)  For each module, a Data Sheet and a Description are
available. Click on the green Icon labeled "Spec" to access
the Data Sheet and click on Help->Help Topics to access the
Module Description.


7)  Fill out the fields as directed in the module Description
and click on GENERATE.

*** NOTE ***
Do not name the Module with a Unified Library Name.  If
you do, the Synthesizer will use the Unified Library XNF file
instead of the one generated by CoreGen.


8)  A VHDL instantiation template (module_name.VHI), a VHDL
behavioral simulation netlist (module_name.vhd), and a Xilinx
Netlist File (.XNF) will be created and copied into the Coregen working director
y.

The VHDL instantiation template contains the component
declaration as well as the Port Map declaration for the
generated module.  It can be Copied and Pasted into your Top
Level VHDL file.  A sample VHI file is listed below:

****** 8 Bit Adder VHDL Instantiation Template ad8.vhi *******

component ad8 port (
	a: IN std_logic_VECTOR(7 downto 0);
	b: IN std_logic_VECTOR(7 downto 0);
	s: OUT std_logic_VECTOR(8 downto 0);
	c: IN std_logic;
	ce: IN std_logic;
	ci: IN std_logic;
	clr: IN std_logic);
end component;

 yourInstance : ad8 port map(
	a => a,
	b => b,
	s => s,
	c => c,
	ce => ce,
	ci => ci,
	clr => clr);

***********************************************


**********  Top Level VHDL file: add8_top.vhd ******

Library IEEE;
use IEEE.std_logic_1164.all;

entity add8_top is
	port (	INA,INB: in  STD_LOGIC_VECTOR (7 downto 0);
		CLK, ce, ci, clr: in STD_LOGIC;
		QOUT: out STD_LOGIC_VECTOR (8 downto 0));
end add8_top;

architecture BEHAV of add8_top is

-- Instantiate the ad8.xnf file.

component ad8 port (
    a: IN std_logic_VECTOR(7 downto 0);
    b: IN std_logic_VECTOR(7 downto 0);
    s: OUT std_logic_VECTOR(8 downto 0);
    c: IN std_logic;
    ce: IN std_logic;
    ci: IN std_logic;
    clr: IN std_logic);
end component;

begin

u1 : ad8 port map (
	    a => ina,
	    b => inb,
	    s => qout,
	    c => clk,
	    ce => ce,
	    ci => ci,
	    clr => clr);

end BEHAV;

******************************************************



NOTES:

- When compiling, read in the design from bottom to top.
- After compiling in Synopsys, do a remove_design on the ad8
  design before writing out the .sxnf file.
- In your run script
  this would appear as:

.
.
.
compile
.
.
.
replace_fpga
.
.
.
remove_design ad8
write -f xnf -h -o "add8_top.sxnf"



End of Record #2116