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SYNPLIFY: How to instantiate PULLUP/PULLDOWN in HDL (Verilog/VHDL)?


Record #2145

Problem Title:
SYNPLIFY: How to instantiate PULLUP/PULLDOWN in HDL (Verilog/VHDL)?


Problem Description:
Keywords: syplify

Urgency: standard

General description: How to instantiate PULLUP/PULLDOWN using
Syplicity's synplify in HDL?

Note:  For CPLD devices, PULLUPs in the IOBs are not user controllable
during normal operation.  These PULLUP resistors are active only during
device programming, power-up, and erase cycle.






Solution 1:

You can instantiate PULLUP/PULLDOWN cells by using the import library
supplied with Synplify. The Synplify Xilinx Macro Libraries contain
pre-defined black-boxes for the Xilinx macros so that you can manually
instantiate them into your design.

For VHDL based designs all one has to do is add the following 2 lines
in the VHDL and instantiate PULLUP/PULLDOWN components. Please look
in the $SYNPLICITY/lib/xilinx/xc4000.vhd on the WS or
C:/synplcty/lib/xilinx/xc4000.vhd on the PC for PULLUP/PULLDOWN
components and its port interface list.  For xc5200 VHDL designs,
use xc4000.vhd "black box" instantiation as an example.
	
	library xc4000;
	use xc4000.components.all;
OR
	library xc3000;
	use xc3000.components.all;

For Verilog designs, just add the xc4000.v file in the source file list
along with the source design file. The xc4000.v file is also in the
$SYNPLICITY/lib/xilinx directory on the WS or C:\synplcty\lib\xilinx.
For xc5200 Verilog designs, use xc4000.v black box instantiation as
an example.



Solution 2:

// Include Synplify Xilinx Macro Libraries
`include "/products/synplify.ver3_0/lib/xilinx/xc4000.v"

module pullup_ex (inbus, enb, com, out_sig);
input [2:0] inbus, enb;
input [1:0] com;
output out_sig;

wire int_sig;

PULLUP U0 ( .O (int_sig));

// Infer tri-state buffers
assign int_sig = (enb[0] == 1'b0) ? inbus[0] & com[0] : 1'bz;
assign int_sig = (enb[1] == 1'b0) ? inbus[1] & com[0] : 1'bz;
assign int_sig = (enb[2] == 1'b0) ? inbus[2] & com[0] : 1'bz;

// glue logic
assign out_sig = com[1] ^ int_sig;

endmodule



Solution 3:

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity pullup_ex is
  port ( inbus, enb : in  STD_LOGIC_VECTOR(2 downto 0);
	 com : in STD_LOGIC_VECTOR(1 downto 0);
	 out_sig : out STD_LOGIC);
end pullup_ex;

architecture xilinx of pullup_ex is

signal int_sig : STD_LOGIC;

begin

U0:  PULLUP port map (O => int_sig);

-- Infer tri-state buffers
int_sig <= inbus(0) and com(0) when (enb(0) = '0') else 'Z';
int_sig <= inbus(1) and com(0) when (enb(1) = '0') else 'Z';
int_sig <= inbus(2) and com(0) when (enb(2) = '0') else 'Z';

-- glue logic
out_sig <= com(1) xor int_sig;

end xilinx;



End of Record #2145