Answers Database

XC9500: How to place a macrocell/signal in low power mode (LOWPWR or PWR_MODE)


Record #2146

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
XC9500: How to place a macrocell/signal in low power mode (LOWPWR or
PWR_MODE)



Problem Description:
Keywords: 9500 macrocell low power lowpwr

Urgency: Standard

General Description:

In Design Manager (XACT-CPLD or M1) there exists a global
option (under Design -> Implement -> Edit Template) to declare macrocells in low
 power mode.  However depending on your design
entry approach - there are several ways to place a particular
macrocell/signal in low power mode in the design itself using
the LOWPWR (for XACT-CPLD) or PWR_MODE (for M1) attributes.

The following are described below:

Resolution #1: Schematic entry
Resolution #2: Foundation XVHDL
Resolution #3: ABEL example

For more information on LOWPWR (XACT-CPLD) and PWR_MODE (M1),
consult the corresponding Libraries Guides.


Solution 1:

XACT-CPLD:

Placing the LOWPWR attribute on a particular symbol requires
both a name and value parameter.

1) Select the particular symbol in question.
2) Open the symbol properties window.
3) Assign NAME -> LOWPWR and VALUE -> ON.


M1:

Placing the PWR_MODE attribute on a particular symbol
requires both a name and value parameter.

1) Select the particular symbol in question.
2) Open the symbol properties window.
3) Assign NAME -> PWR_MODE and VALUE -> LOW.

*Because declaring attributes varies between schematic
 capture tools - please consult the appropriate interface
 guide for the correct procedure in declaring attributes.



Solution 2:

XACT-CPLD:

-- Foundation XVHDL example of using the LOWPWR attribute

library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR;
--Package attributes contains declarations of the Metamor --specific synthesis a
ttributes.
use METAMOR.attributes.all;

entity flop is
   port (clk, din, reset: in std_logic ;
	 dout : out std_logic);
end flop;

architecture PWRTEST of flop is
--  D F/F with asynchronous Reset

   signal DUMMY: std_logic;

   attribute LOWPWR: string;
   attribute LOWPWR of DUMMY: signal is "on" ;
       		
begin
   process (CLK, RESET)
   begin
     if RESET='1' then	--asynchronous RESET active High
	DUMMY <= '0';
     elsif (CLK'event and CLK='1') then  --CLK rising edge
	DUMMY <= DIN;
     end if;
   end process;

   Dout <= DUMMY; -- passes the ouput of FF to the opad
		  -- this dummy signal is created to be
		  -- able to put a lowpwr attribute
		  -- on the FF whose output is also
		  -- a top-level port
end PWRTEST;


M1:

-- Foundation XVHDL example of using the PWR_MODE attribute

library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR;
--Package attributes contains declarations of the Metamor --specific synthesis a
ttributes.
use METAMOR.attributes.all;

entity flop is
   port (clk, din, reset: in std_logic ;
	 dout : out std_logic);
end flop;

architecture PWRTEST of flop is
--  D F/F with asynchronous Reset

   signal DUMMY: std_logic;

   attribute PWR_MODE: string;
   attribute PWR_MODE of DUMMY: signal is "low" ;
       		
begin
   process (CLK, RESET)
   begin
     if RESET='1' then	--asynchronous RESET active High
	DUMMY <= '0';
     elsif (CLK'event and CLK='1') then  --CLK rising edge
	DUMMY <= DIN;
     end if;
   end process;

   Dout <= DUMMY; -- passes the ouput of FF to the opad
		  -- this dummy signal is created to be
		  -- able to put a pwr_mode attribute
		  -- on the FF whose output is also
		  -- a top-level port
end PWRTEST;



Solution 3:

In ABEL, there exist the following property statement:

xepld property 'pwr low <signal_1> <signal_2> ...'

Which will place signal_1 and signal_2 in low power mode,
the remaining signals in the design in STD power mode.

Further explanation on this and other property/sytax
statements are found under (Xilinx XAPP076) -- Using ABEL
with Xilinx CPLD's.


"XABEL example of using the xepld property PWR statement:

module PWRTEST
Title 'pwrtest'

" D F/F with asynchronous Reset

Declarations

DIN PIN;
CLK PIN;
RESET PIN;
DOUT PIN istype 'reg';

xepld property 'pwr low dout';

Equations

DOUT.CLK = CLK;
DOUT.ACLR = RESET;
DOUT := DIN;

end




Solution 4:

In M1, "LOWPWR=ON|OFF" is replaced by "PWR_MODE=LOW|STD".
In XABEL (EDIF flow) use:
  XILINX PROPERTY 'PWR_MODE=LOW|STD signal_name...';

(xepld property syntax is obsolete in M1.)



End of Record #2146