Answers Database

M1.3 VERILOG-XL: Toggling global reset and tri-state using M1 mixed modeUnified simulation libraries.


Record #2189

Product Family:  Software

Product Line:  Cadence

Problem Title:
M1.3 VERILOG-XL: Toggling global reset and tri-state using M1 mixed
modeUnified simulation libraries.



Problem Description:
Keywords: global reset GSR GTS GR PRLD startup ngd2ver concept verilog synergy

The Verilog Unified Library simulation models shipped in
M1.3.7 support a new feature--the ability to do a mixed mode
Concept/Synergy functional simulation using a test fixture  file which can also
be used for timing simulation with a few
minor changes.	This is the first time this capability has
ever been offered.

Note that this feature was not available in the M1.2.11
Alliance Pre-release.  The first release of this feature
in the Cadence interface libraries for Concept and Verilog
was in the M1.3.6 BETA release.  (Synergy library support
is available from Cadence Design Systems only.)

The accompanying support in the NGD2VER netlister will be
available in the full M1.3.7 release in July 1997.

The methodology is described below.


Solution 1:

HDL Direct UNIFIED LIBRARY Functional Simulation (Cadence
Concept and Concept/Synergy Mixed Mode Designs only)

*************************************************************
***  WITHOUT Startup: ***
*************************************************************

.V from HDL Direct:
==================
No modification to the .V file produced by HDL Direct,
except that you must make sure that the "ARCHSIMLIB"
macro in the .V file points to the new beta M1.3.6
Verilog Unified libraries:

   `uselib ARCHSIMLIB <path_to_M1.3.6_Verilog_libs>


.TV testbench for HDL Direct netlist simulation of designs
==========================================================

The .TV testbench for HDL Direct netlist simulation of designs
must be modified as follows:

1. 4k/e/ex/xl designs:

  - You can use the same testbench for

   a. Unified Library simulation,
   b. post-NGDBUILD functional simulation, and
   c. timing simulation

  Add the following to your test fixture file:

<INPUT>
  reg GSR; 			// if design has flip flops
				// or latches
  `define GSR_SIGNAL test.GSR

  reg GTS;			// if design has output
				// buffers
  `define GTS_SIGNAL test.GTS

   ...


  initial
    begin

// Toggle global set/reset

    `GSR_SIGNAL = 1;	   // or GSR = 1;
    `GTS_SIGNAL = 0;	   // or GTS = 0;
   #100
    `GSR_SIGNAL = 1;

  ...
</INPUT>


*************************************************************** WITH  Startup: *
**
*************************************************************

1. HDL Direct UNIFIED LIBRARY Functional Simulation
===================================================

4k/e/ex/xl:

  Add the following to your .V file:

<INPUT>
  `define GSR_SIGNAL test.uut.gsrin

  wire GTS;
  `define GTS_SIGNAL test.GTS	 <------- must be added
					  manually

  ...


initial
  begin

     <GSR_controller_port_name> = 1;
      force `GTS_SIGNAL = 0;	// set GTS inactive using the
				// user-declared GTS wire name

     #100
     <GSR_controller_port_name> = 0;
  ...

</INPUT>


POST-NGDBUILD Functional Simulation,
POST-Map Timing Simulation, and
POST-Route Timing Simulation
===================================================

Required changes to your .V file:

 - Add the design instance scope to the name of the GTS
   signal, if unconnected:

<INPUT> `define GTS_SIGNAL test.uut.GTS     </INPUT>

- Comment out GSR_SIGNAL definition (full support for
  GSR connections exist when a port is connected to
  the GSR pin on the STARTUP component).

<INPUT>   `define GSR_SIGNAL test.uut.gsrin  </INPUT>

The rest stays the same:

<INPUT>
initial
  begin

     <GSR_controller_port_name> = 1;
      force `GTS_SIGNAL = 0;	// set GTS inactive using the
				// user-declared GTS wire name

     #100
     <GSR_controller_port_name> = 0;
  ...

</INPUT>






End of Record #2189