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What are the differences between Synopsys FPGA Compiler and Design Compiler?


Record #2197

Product Family:  Software

Product Line:  Synopsys

Problem Title:
What are the differences between Synopsys FPGA Compiler and Design
Compiler?



Problem Description:
Keywords : Design Compiler, FPGA Compiler, Synopsys

Urgency : Standard

Description : What are the differences between Synopsys FPGA
Compiler and Design Compiler?


Solution 1:

When targeting an FPGA, FPGA Compilier typically does an
overall better job with sythesis and reporting than Design
Compiler, especially if you are targeting an xc4000 Device.
This is a list of some of the features and differences of
both compilers.

Here is a list of some of the features of both :

- High degree of support of HDL Language
- Automatic Inference of XBLOX Modules
- State Machine encoding, re-encoding (including one-hot)

Here is a list of some of the features availible in FPGA
Compiler but not Design Compiler :

- Read and Write XNF files
- Optimize Existing XNF files
- Mapping of logic into CLBs and IOBs
- Analyze post place & route delay information
- Automatic generation of timing specs for placement & routing
tools
- Xilinx specific optimization algorithms
- Synthesis to FPGA CLB/IOB and LUT Structures
- High acuracy area/speed reporting for FPGAs

Note:  FPGA Compiler users should only write out XNF (.sxnf)
files for implementation into the Xilinx tools.  The EDIF
format is not supported from FPGA Compiler.  Conversely, Design
Compiler users should only write out EDIF (.sedif) files for
implementation into the Xilinx tools.  The XNF format is not
supported for Design Compiler.



End of Record #2197