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HDL Synthesis guide pp 1-8 & 1-9: Location of design files is wrong.


Record #2200

Problem Title:
HDL Synthesis guide pp 1-8 & 1-9: Location of design files is wrong.


Problem Description:
Keywords: HDL, synthesis, guide, verilog


Solution 1:

On pages 1-8 and 1-9 of the HDL Synthesis For FPGAs lists some example design fi
les for verilog.  On page 1-10 the instructions to access these files instructs
to ftp to xilinx.www.com and change to the xsi_hdl directory.  This directory no
 longer exists.  Instead use:

ftp ftp.xilinx.com/pub/swhelp/synopsys



End of Record #2200