Answers Database

M1.4: CADENCE LEAPFROG--Simulating VHDL designs in the Xilinx M1 release


Record #2202

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4: CADENCE LEAPFROG--Simulating VHDL designs in the Xilinx M1 release


Problem Description:
Keywords: vhdl vital leapfrog simulation

Urgency: standard

General Description:
Besides their Verilog simulator, Verilog-XL, Cadence also ships
a VHDL simulator called Leapfrog.


Solution 1:


VHDL simulation in M1 is supported by the VITAL-compliant
NGD2VHDL netlister and the associated M1 VITAL SIMPRIM
simulation libraries.

Both the netlister and the libraries (source code format
only) are shipped with the Xilinx M1 core software, and are
supported by Xilinx.

To generate a simulation netlist, the following
flows may be used:

post-NGDBUILD functional simulation:

  ngdbuild design
  ngd2vhdl -tb design.ngd --->	gives you .vhd file

post-route Timing simulation:

  map  design
  par design designr
  ngdanno designr
  ngd2vhdl -tb designr

For instructions on compiling the VHDL SIMPRIM libraries
for Leapfrog, please consult the Cadence Openbook online
documentation.



End of Record #2202