Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


PPR 5.x: Possible cause of ERROR 9929


Record #2205

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
PPR 5.x: Possible cause of ERROR 9929


Problem Description:
Keywords: ppr global buffer tbuf 9929
Urgency:  Standard

General Description:
You may get the following error:

*** PPR: ERROR 9929:
	  Clock pins not sourced by global buffers, and/or TBUF input pins
	  and/or T pins cannot be completely routed.
	  An LCA file will be generated to permit analysis of this problem.
	  Possible resolutions are discussed below by load pin type.


Solution 1:

1. Check for clock pins and tbuf's as suggested in the error message. If everyth
ing is OK, turn ON xblox optimization.
If you are running the tool from DOS/UNIX prompt, use '-b' option with xmake.
(ex: xmake -p 5204pq100-6 -x -b design_name)

If running Design Manager(windows), do this:
Design -> Implement -> edit Template(Implementation) -> Optimization -> Merge Fl
ip-Flops into I/Os.




End of Record #2205

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents