Answers Database
M1 map: What are the rules for merging FFs into an IOB with the MAP -pr b switch?
Record #2207
Product Family: Software
Product Line: FPGA Implementation
Problem Title:
M1 map: What are the rules for merging FFs into an IOB with the MAP -pr
b switch?
Problem Description:
Keywords: map, -pr b, IOB, FFs, flip-flops
Urgency: Standard
with the -pr b switch to pack registers into the IOB, move
registers into the IOBs?
Solution 1:
Under the following circumstances, a CLB FF will get merged
into an IOB when map is invoked with the -pr b option :
1. The D pin of the FF must be connected to the output of an
IBUF or the Q pin must be connected to the input of an
OBUF or an OBUFT. In the case of the FF connected to the
input of an OBUF or OBUFT, there must be only ONE load on
this signal.
The output of the CLB FF can only drive a single output
net. For example, if the output feeds back into the input
of the CLB FF, the FF will not be merged, because this
counts as an additional load.
For the 4000EX/XL this applies to
non-I/O latches as well flip-flops.
2. The IOBs must have input or output flip-flops. The XC5200
architecture does NOT have IOB flip-flops.
3. There is no CLB external net attribute (X flag) attached
to the signal between the flip-flop and the I/O buffer.
4. The flip flop does not use an asynchronous set or reset
signal.
5. For all 4K devices, a flop/latch will not be added to an
IOB if it is part of a macro.
6. For all 4K and 3K devices, a flop/latch will not be added
to an IOB if it has a BLKNM or LOC conflict with the IOB.
7. For 4K devices, a flop/latch will not be added to an IOB
if its control signals (clock or clock enable) are not
compatible with those already defined in the IOB. This is
for those cases where
- a flop (latch) is already in the IOB, and a latch (flop)
needs to be added, or
- the 4kEX/XL Output MUX is being used, or
- a flop already exists in the IOB that is clocked by a
different clock signal.
8. In XC4000EX, if a constant 0 or 1 is being driven on the
IOPAD, a flop/latch with a CE will not be added to the
input side of the IOB.
End of Record #2207
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |