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VERILOG-XL Environment Error: Parent node XXXXX not found


Record #2212

Product Family:  Software

Product Line:  Merged Core

Problem Title:
VERILOG-XL Environment Error: Parent node XXXXX not found


Problem Description:
Keywords:  parent node verilog ngd2ver error

Urgency:  standard

General Description:

A "Parent node not found" error may be seen when invoking
Verilog-XL with the +venv option on a Verilog netlist
containing escaped names (like those generated by NGD2VER
versions m1.1.1a through m1.3). The error is usually seen
in the command tool or shell window from which you invoke
the program.

The +venv option is used to invoke the Verilog-XL
Environment.  The Verilog-XL Environment is a graphical
environment which links up a graphical interface to Verilog-XL
simulator to an EMACS-based Verilog Language Sensitive Editor
(LSE) and the cWaves waveform viewer.

The program issuing the error message is actually the LSE
engine, lemacs. lemacs fails to read in the source code if
the code contains certain special characters.

As for the reference to a "parent node" not being found:
these errors come from net names containing extra "."
period symbols in net names generated by NGD2VER.  Such
net names may be generated when the Xilinx M1 Core
Tools combines local reset and tri-state signals with their
global counterparts and creates a new net name for the result
When this occurs, you will see names like,

  \p1$i9/GTS.AND.0

Notice that this name is escaped with a "\" because it
contains the Verilog-illegal character, "/". (See Xilinx
Solution 1535 for a list of LEGAL Verilog characters.)
It also contains a number of periods, which in Verilog syntax
are interpreted as hierarchy separators. Because of the
lemacs bug, all periods in the escaped Verilog name are
interpreted as hierarchy separators, and an error like,

  "Parent node	\p1$i9/GTS.AND not found "

is issued. What is happening here is that LEMACS is mistaking
\p1$i9/GTS for a "parent node", or net which drives another
net, when in fact it is not an actual net name--only part of
one.



Solution 1:


The problem is a known Cadence bug with the Verilog
Language Sensitive Editor's (LSE) TMS subprogram (PCR
#150228, reported against 9404).  Cadence has not committed
to fixing this bug.

As a workaround, you can replace all the "." symbols in
your netlist with "_".	The disadvantage of doing this
is that you lose the ability to access the nets in your
design hierarchically through cWaves.



End of Record #2212