Answers Database

CONCEPT HDL Direct Error: Invisible property SIG_NAME="GR \G": Illegal HDL name: illegal character after signal or port name


Record #2216

Product Family:  Software

Product Line:  Cadence

Problem Title:
CONCEPT HDL Direct Error: Invisible property SIG_NAME="GR \G": Illegal
HDL name: illegal character after signal or port name



Problem Description:
Keywords: concept hdl direct warning invisible property
signame \g illegal character xblox x-blox

Urgency:  standard

General Description:

You may get a warning similar to the following
when saving an XBLOX design in Concept with HDL Direct
enabled:

Warning: Invisible property SIG_NAME="GR \G":
	Illegal HDL name: illegal character after signal or
	port name

From Chapter 2, page 11, of the Xilinx FPGA Designer
(Concept) UserGuide:

HDL Direct Warnings You Can Ignore
----------------------------------
Warning: page <page#> instance <instance> port <port> mode
			<mode> cannot be left unconnected




Solution 1:



You can ignore this error message if the instance is an
X-BLOX component, AND the port has been *intentionally* left
unconnected. For example, if the STYLE property on a SHIFT
register is set to CIRCULAR, you MUST leave the LS_IN input
unconnected.  The types of instances for which
this warning appears are typically XC4000 flip-flops,
latches, or output buffers.

If, in fact, you have erroneously left unconnected a port which should have been
 connected, the X-BLOX software will
error out on this condition later in the flow.

The warning is a side effect of processing a SCALD-compliant
design in Concept with HDL Direct mode enabled. HDL
Direct and SCALD handle global signal names differently.
In SCALD, a global signal has \G appended to end of the
signal name, whereas HDL Direct global signal names must
have a "/" prefix.

HDL Direct is not recognizing a signal which
has been designated as a global signal according to SCALD
methodology, however the condition reported by this
warning does not adversely affect the netlist generation step
in Xilinx FPGA Designer for Concept.



End of Record #2216