Answers Database

M1 MAP/NGDBUILD, LogiBLOX: Pin mismatch between block ... at pin ....


Record #2234

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1 MAP/NGDBUILD, LogiBLOX: Pin mismatch between block ... at pin ....


Problem Description:
Keywords: map, ngdbuild, unexpanded, pin mismatch, logiblox

Urgency: standard

General Description:

WARNING:0 - Pin mismatch between block 'addsub1', TYPE='addsub32',
and file '/xilinx/fpga/design/addsub32.ngo' at pin 'A<31>'




Solution 1:

If the above warning or error occurs while running NGDBUILD on
a design that contains LogiBLOX, then often the cause is that
the bus pin dimension seperator on the LogiBLOX is different that the bus pin di
mension seperator of the block that contains
it (i.e.,  "mybus<3>" is not equal to "mybus(3)" )

The solution is to ensure that a consistent bus pin dimension
seperator is used. In LogiBLOX, this can be done by either
choosing the correct Vendor in Setup, or choosing the correct
Bus Notation in Setup. You can open the logiblox.ini file to
see what settings you chose previously.




Solution 2:

Make sure that the pin names are the same between the
block that contains the LogiBLOX and the LogiBLOX module
itself. If using a HDL tool, paste the contents of the
VHDL or Verilog template (.vhi and .vei, respectively) into
your code to instantiate the module.
If you are making a symbol for the LogiBLOX module (necessary
for some schematic entry tools), make certain that pin names
match precisely.
The pin names should be in upper case, and the names of the
pins can be found in the .mod file. The bus notation is found
in the .ini file, if you are uncertain which options you chose.




End of Record #2234