Answers Database

M1: Concept XC7000 ifdx1 input register will preload to "0" in Verilog Unified Library functional simulation


Record #2259

Product Family:  Software

Product Line:  Cadence

Problem Title:
M1: Concept XC7000 ifdx1 input register will preload to "0" in Verilog
Unified Library functional simulation



Problem Description:
Keywords: verilog-xl, concept, ifdx1, 7300, preload, 7000,
hdl direct, unified, initial

Urgency: standard

Reference: 17958


General Description:

The IFDX1 symbol in the 7000 library currently preloads to
"0" in Verilog simulation using the Unified libraries (via
HDL Direct). It should preload to "1".


Solution 1:

You need to do a simprim based simulation (run concept2xil,
ngdbuild, ngd2ver) instead, or use a different flop in
schematic if the initial preload value is significant.




End of Record #2259