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FPGA Express v1.1: Does not allow Verilog parameters used as indices forarrays


Record #2270

Product Family:  Software

Product Line:  Merged Core

Problem Title:
FPGA Express v1.1: Does not allow Verilog parameters used as indices
forarrays



Problem Description:
Keywords: FPGA Express, Verilog, Syntax, v1.1

Urgency: Standard

general description:

A legitimate syntax for Verilog is to assign a parameter to an indexed array
in the following manner:

parameter indexname;
.
.
.


assign a=b[indexname] ;

where 'indexname' is defined as a parameter.

This is currently not supported by FPGA Express v1.1


Solution 1:

Replace the paramter in the array index with the actual value.	So, in the
example above, if indexname had been set to '3', then the assign statement
would become:

assign a = b[3];



Solution 2:

If replacing the parameter with the actual value is not convienent,
then logically 'AND' with '1' the expression with the paramter. In the
example above:


assign a = b[indexname];

would become:

assign a = b[indexname] & 1'b1;



End of Record #2270