Answers Database

Cadence board-level simulation M1: The -pf option not supported in Design Manager


Record #2278

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
Cadence board-level simulation M1: The -pf option not supported in
Design Manager



Problem Description:
KEYWORDS: board, simulation, cadence, pin, timing

URGENECY: Standard

GENERAL DESCRIPTION:
Cadence designs need the "-pf" option when running timing
simulation flow if a board-level model is to be created by
XIL2CDS.  The "-pf" option generates a .pin file
needed for Cadence board-level simulation.  This option is
not automatically used when going through the flow engine.


Solution 1:

From the Design Manager menu, select Utilities->Template Manager.
In the Template Manager:

   Select - Implementation Templates
   Select - <Family Type>
   Select - Customize

In the Customize dialog:

   For Program Name enter    - ngd2ver
   For Program Options enter -	-pf
   Click - Set
   Click - OK

In the Options dialog, make sure that the Implementation template
that you customized is selected, also make sure that you have
"Produce Timing Simulation Data" selected. When the Flow Engine
runs the Timing step, the -pf option will be passed to the ngd2ver
command and the pin file will be created in the revisions directory.

To move the pin file to your netlist directory you need to copy it using
an Operating system command line or File Browser.



End of Record #2278