Answers Database

HDL timing simulation: compiling testbench reveals port mismatches


Record #2283

Product Family:  Software

Product Line:  Merged Core

Problem Title:
HDL timing simulation: compiling testbench reveals port mismatches


Problem Description:
Keywords: VHDL, Verilog, testbench, simulation, ports, DOWNTO

Urgency: Hot

General Description:

Compiling your unit-under-test design from NGD2VER or NGD2VHDL along with your t
estbench reveals mismatches on bused ports.


Solution 1:

This problem comes about when your unit under test has top-level ports that
are defined as LSB-to-MSB, e.g.,

   Verilog:  input [0:7] A;
   VHDL:     A: in STD_LOGIC_VECTOR (0 to 7);

The Xilinx design database does not keep track of the direction in which
buses were defined in the original design.  When NGD2VER or NGD2VHDL writes
out a structural timing Verilog or VHDL description, all buses are written
as MSB-to-LSB, e.g.,

   Verilog:  input [7:0] A;
   VHDL:     A: in STD_LOGIC_VECTOR (7 downto 0);

If your ports were originally defined as LSB-to-MSB in your original design
and testbench, this results in a port mismatch when the testbench is
compiled for timing simulation.  There are two ways to work around this
problem:

1. In the testbench, modify the instantiation of the unit under test so
   that all ports are defined as MSB-to-LSB for timing simulation, OR

2. Define all ports as MSB-to-LSB in the original design and testbench.



End of Record #2283