Answers Database

M1.3 MAP: Unable to pack CLB driven by 2 external signals with DFFs sharing an SR signal.


Record #2291

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.3 MAP:  Unable to pack CLB driven by 2 external signals with DFFs
sharing an SR signal.



Problem Description:
Keywords:  map, pack, dff, sr, rloc, hmap, h1, di, din, hlut, h-lut

Urgency: standard

General Description:  Map is unable to combine a CLB driven
by 2 external signals with DFFS sharing the same SR control
signal.  This is a valid CLB combination that requires
Map to use the G-LUT to feed the H-LUT, and to also use the H1
and DIN pins, since SR is already being used.


Solution 1:

This problem has been documented as bug number 12429.

Please refer to the Xilinx M1.3 Conversion Guide application
note for more detailed information concerning unsupported
CLB combinations.

One possible workaround would be to manually create the
desired CLB configuration in EPIC, converting it into a
physical macro, then instantiating the macro in your design.

For more information on creating physical macros, refer to
the (Xilinx Manual EPIC Design Editor Reference/User Guide).

Bug Reference #:  12429
r_stm/kl



End of Record #2291