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M1.3, M1.4 MAP: 'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on CLB .... in RPM ....'. The design is too large for the given device and package (c an't fit design).


Record #2312

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.3, M1.4 MAP:	'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on
CLB .... in RPM ....'.  The design is too large for the given device and package
(c
an't fit design).



Problem Description:
Keywords:  map, fit, optimize

Urgency:  Hot

General Description:  Map fails with the following error:

<OUTPUT>
The design is too large for the given device and package.
Please check the Design Summary section for more information.
If your design requires more CLBs and/or IOBs that the
current target device, choose a new device accordingly.
Alternatively, you may try to redesign your logic so that it
does not require as many resources.
</output>

NOTE:  Although the design will not fit the target
device, an NCD file is still written out to allow the
user to do preliminary timing and mapping analysis if
desired.


Solution 1:

If you must use the current target device, the following
suggestions may help you fit the design.

1. Turn off register ordering by using the "-r" command-line
option.  Removing the need to physically map data-register
flip-flops in order affords more mapping flexibility, which
may allow more logic to fit into the design.

2. Set the environment variable LATE_BUS_PAIRS (e.g.,
<input> "setenv LATE_BUS_PAIRS" on SPARCstations).  </input>

This disables some of MAP's attempts to do flip-flop/TBUF
alignment and defers the job to PAR.  This may give MAP
more flexibility.  However, adding this burden to PAR
may prevent PAR from running successfully.

3. Set the environment variable NOFMAPS (e.g.,
<input> "setenv NOFMAPS" </input>
on SPARCstations).

This tells MAP to disregard all user map information
(FMAPs and HMAPs).  NOFMAPS is not recommended if the design
contains mapped carry logic.

4. Use the "-pr i|o|b" (e.g., "-pr b") option to merge
flip-flops into IOBs (input, output, or both).	This may
decrease CLB usage.

5. Optimize the design for area with the "-os area" option.*

6. Optimize the design with high effort using the "-oe high"
option.*

7. Use "-k" to map logic into five-input functions where
applicable.

*Suggestions 5 and 6 may cause some nets to be inaccessible
in timing simulation.



Bug reference #:  16845
r_stim/kl



Solution 2:

The other possibility is that your design contains logic
with location constraints (either LOCs or RLOCs) that
constrain its logic to some number of rows that exceeds
the number of rows of CLBs available in your target device.
In other words, the macro is too "tall" for the target device.

Options:
--------

1. Target a "taller" part (one with more roews)
2. If the error is due to restrictions imposed by LOC
constraints, remove these from the design and reprocess.
(You may suffer a performance hit.  In some cases this may
make the design harder to route, as well.

3. If the error is due to restrictions imposed by RLOC
(relative location) constraints, try  specifying the -ir
option when you run Map so that Map does not use the RLOCs
to generate an RPM.

Again, you will likely suffer a performance hit or make the
design harder to route by doing this.




End of Record #2312