Answers Database

Design Manager M1: Configuration Template does not support 4kex & 4kxl higher-order addresses


Record #2321

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
Design Manager M1: Configuration Template does not support 4kex & 4kxl
higher-order addresses



Problem Description:
Keywords: XC4000EX, XC4000XL, master parallel mode, bitgen, AddressLines

Urgency: Standard

General Description:

The Configuration Template Manager does not have a built-in option to
enable the highest order address lines for XC4000EX configuration in
Master Parallel Mode.


Solution 1:

From the Design Manager menu, select Utilities->Template Manager.
In the Template Manager:

   Select - Configuration Templates
   Select - <Family Type>
   Select - Customize

In the Customize dialog:

   For Program Name enter:     bitgen
   For Program Options enter:  -g AddressLines:22
   Click - Set
   Click - OK

In the Options dialog, make sure that the Configuration template
that you customized is selected.  When the configuration step is run,
the -g AddressLines:22 option will be passed to the bitgen command.
When the bit file is loaded into the FPGA, the upper address lines will
become valid after the first frame is loaded.

Note: The upper address lines will need pull-down resistors (~5k) to
ensure that you start loading from address 0.  The pull-down resistors
hold the  lines at 0 until the first frame is loaded.







End of Record #2321