Answers Database

M1.3/M1.4 Map: How to ignore RLOCs / Map does not have a built-in ability to ignore RLOCs completely (or, the meaning of the MAP "-ir" option)


Record #2332

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.3/M1.4 Map:  How to ignore RLOCs / Map does not have a built-in
ability to ignore RLOCs completely (or, the meaning of the MAP "-ir" option)



Problem Description:
Keywords: Map, ignore RLOCs, -ir, FPGA

Urgency: Standard

General Description:
Reference Number: 13552
In XACT, PPR had an option that allowed you to ignore RLOC
constraints in an input design file (ignore_rlocs = true).

Map does not have a equivalent option.

The closest you can get to ignoring RLOCs in the M1 Mapper
is to specify the -ir switch.  This switch tells Map not to
use RLOCs to generate RPMs.  What this means is that Map will
still use the RLOCs in the design to map RLOC'd logic INTO
the same CLB, but will not preserve the relative location
BETWEEN different CLBs.  As a result, you may still get
errors about not being able to combine symbols having the
same RLOC.


Solution 1:

If your design already has RLOCs in it, and you would like
to ignore them, you can either go to your original design and
remove them (i.e., delete them from your schematic or
constraint file), or you can manually edit your design_name.edif file.


CAUTION:

Removing _ALL_ RLOC constraints from your design may cause
problems if there is carry logic in your design.  In that
case, it is recommended that you simply run Map with the -ir
option instead so that RLOCs are still used to map logic
into the same CLB.




Solution 2:

Alternatively, you could copy the xnfin.prp file from the
$XILINX/data directory into the data subdirectory of a separate
user directory.  Define an environment variable called
"MYXILINX" in your Xilinx setup file, and set it to point to
this user directory.

Edit the xnfin.prp and remove the line that starts with the
word, "RLOC":

RLOC	       string	   RLOC     string	  TRUE


Example:

Say we name the user directory "/tools/xilinxuser".

Create a subdirectory called "data" here and copy the
xnfin.prp file from the $XILINX/data directory to
"/tools/xilinxuser/data".  Remove the RLOC record in the
xnfin.prp file as indicated above and save the file.

Now when NGDBUILD reads in the design, it will use the
xnfin.prp in your MYXILINX/data directory and not translate
any of the RLOC constraints specified in the input design.


PLEASE NOTE!

The same caution indicated in Resolution #1 applies here about
potential problems with logic associated with carry logic
when RLOCs are totally ignored.



End of Record #2332