Answers Database

M1.3 MAP: "Unable to obey design constraints" errors / Unsupported CLB combinations involving dual output logical components (DPRAM, RAM16x2)


Record #2345

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.3 MAP: "Unable to obey design constraints" errors / Unsupported CLB
combinations involving dual output logical components (DPRAM, RAM16x2)



Problem Description:
Keywords: dual port ram di unsupported pack merge dpram ram16x2

Urgency: standard

General Description:
CLB configurations involving the F and G combinational
outputs from the same CLB driving a 2- or 3-input function
that could fit into the H LUT are not supported by the M1.3
Mapper.

There is no one error message that is symptomatic of the
Mapper to handle such configurations, but most likely it
would be one that starts with,

"Unable to obey design constraints which require the
combination of the following symbols into a single
CLB"

This configuration is illustrated in the following figure:

F and G combinational outputs from the same CLB drive 2- or 3-input
LUT that could be packed into the H LUT.

The same problem presents itself when trying to map a
16x2 RAM with additional logic that could fit into an H-LUT.


Solution 1:

The only workaround available is to create the desired CLB
configuration in EPIC, generate a physical macro from it,
and instantiate it into your design.

For more information on creating physical macros, refer to
the (Xilinx Manual EPIC Design Editor Reference/User Guide).



End of Record #2345