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SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?


Record #2379

Problem Title:
SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?


Problem Description:
Keywords: Verilog, VHDL, synplify

Urgency: Standard

General Description:  How to lock down I/O pins in the HDL using
Synplicity's synplify?


Solution 1:

// Assigning I/O locations through a constraints file (.sdc)
// Verilog code

module iob_loc_ex (CLK, A, B, O);
input CLK;
input [3:0] A;
input [3:0] B;
output [3:0] O;

reg [3:0] Q;

    always @ (posedge CLK)
    begin
	  Q <= A;
    end

// token logic
assign O = Q & B;

endmodule


# Vendor specific constraints are passed in an .sdc file

define_attribute CLK xc_loc "P13"
define_attribute {A[3:0]} xc_loc "P19,P20,P23,P24"
define_attribute {B[3:0]} xc_loc "P25,P26,P27,P28"
define_attribute {O[3:0]} xc_loc "P48,P49,P50,P51"


#-- TCL script
#-- Assigning I/O locations through a constraints file (.sdc)

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -constraint "iob_loc_ex.sdc"
add_file -verilog "iob_loc_ex.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "iob_loc_ex.xnf"
project -run

#end TCL



Solution 2:

-- Assigning I/O locations into HDL
-- VHDL code

library IEEE;
use IEEE.std_logic_1164.all;

entity iob_loc_ex is
    port (CLK : in STD_LOGIC;
	  A, B :  in STD_LOGIC_VECTOR (3 downto 0);
	  O : out STD_LOGIC_VECTOR (3 downto 0));

attribute xc_loc : string;
attribute xc_loc of CLK : signal is "P13";
attribute xc_loc of  A	: signal is "P19,P20,P23,P24";
attribute xc_loc of  B	: signal is "P25,P26,P27,P28";
attribute xc_loc of  O	: signal is "P48,P49,P50,P51";
end iob_loc_ex;

architecture xilinx of iob_loc_ex is

signal Q : STD_LOGIC_VECTOR (3 downto 0);

begin
U0: process (CLK)
    begin
	if (CLK'event and CLK='1') then
	    Q <= A;
	end if;
    end process;

-- token logic
O <= Q and B;

end xilinx;


#-- TCL script
#-- Assigning I/O locations into HDL

set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -vhdl -lib work "iob_loc_ex.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "iob_loc_ex.xnf"
project -run

#end TCL



Solution 3:

// Assigning I/O locations into HDL
// Verilog code

module iob_loc_ex (CLK, A, B, O);
input CLK /* synthesis xc_loc="P13" */;
input [3:0] A /* synthesis xc_loc="P19,P20,P23,P24" */;
input [3:0] B /* synthesis xc_loc="P25,P26,P27,P28" */;
output [3:0] O /* synthesis xc_loc="P48,P49,P50,P51" */;

reg [3:0] Q;

    always @ (posedge CLK)
    begin
	  Q <= A;
    end

// token logic
assign O = Q & B;

endmodule


#-- TCL script
#-- Assigning I/O locations into HDL

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -verilog "iob_loc_ex.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "iob_loc_ex.xnf"
project -run

#end TCL



Solution 4:

-- Assigning I/O locations through a constraints file (.sdc)
-- VHDL code

library IEEE;
use IEEE.std_logic_1164.all;

entity iob_loc_ex is
    port (CLK : in STD_LOGIC;
	  A, B :  in STD_LOGIC_VECTOR (3 downto 0);
	  O : out STD_LOGIC_VECTOR (3 downto 0));
end iob_loc_ex;

architecture xilinx of iob_loc_ex is

signal Q : STD_LOGIC_VECTOR (3 downto 0);

begin
U0: process (CLK)
    begin
	if (CLK'event and CLK='1') then
	    Q <= A;
	end if;
    end process;

-- token logic
O <= Q and B;

end xilinx;


# Vendor specific constraints are passed in an .sdc file

define_attribute CLK xc_loc "P13"
define_attribute {A[3:0]} xc_loc "P19,P20,P23,P24"
define_attribute {B[3:0]} xc_loc "P25,P26,P27,P28"
define_attribute {O[3:0]} xc_loc "P48,P49,P50,P51"


#-- TCL script
#-- Assigning I/O locations through a constraints file (.sdc)

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -constraint "iob_loc_ex.sdc"
add_file -vhdl -lib work "iob_loc_ex.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "iob_loc_ex.xnf"
project -run

#end TCL



End of Record #2379