Answers Database

M1, VERILOG: What is needed to support Verilog simulation of Synopsys and other third party platform designs


Record #2432

Product Family:  Software

Product Line:  Cadence

Problem Title:
M1, VERILOG: What is needed to support Verilog simulation of Synopsys
and other third party platform designs



Problem Description:
Keywords: synopsys, verilog, simulation

Urgency: standard

General Description:
What is needed to support Verilog simulation of Synopsys and
other 3rd party entry designs in the M1 release?


Solution 1:

A generic Verilog HDL interface is supplied with the M1 core
software, consisting of the NGD2VER netlister, and generic
SIMPRIM-based Verilog simulation libraries.  This supports
post-NGDBUILD functional simulation and post-route timing
simulation.

When targeting a Verilog-XL simulation, it is recommended
that the -ul option be specified when running the NGD2VER
netlister.  When the -ul option is specified, NGD2VER will
write out a `uselib directive to the output .v file directing
Verilog-XL to the location of the simulation libraries.



End of Record #2432