Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


TRCE M1.3: Paths that include RAMs deeper than 16 address cells not analyzed.


Record #2443

Product Family:  Software

Product Line:  Merged Core

Problem Title:
TRCE M1.3: Paths that include RAMs deeper than 16 address cells not
analyzed.



Problem Description:
Keywords: trce, ram, analyzed

Urgency: Standard

General Description:

TIMESPECs that include RAMs in TIMEGRPs show only some or none of the
paths analyzed.  This can happen when a Timing Group of RAMs is
infered with the use of a TNM (Time Name).


Solution 1:

The RAM BEL is typically named by the name of the RAM output NET name.
For example, if the output NET of a ram16x1s is named "N$1", then the
resulting BEL name for the RAM primitive will also be "N$1".

For RAM primitives that are deeper than 16 address locations, two
Function Generators are needed to implement the RAM.  Each of the FGs
will get a unique BEL name.  For example, if the name of the RAM
output NET is "N$2", then the two BEL names for the RAM will be:

"BEL_N$2.F" and "BEL_N$2.G"

If the .ucf file used the following constraints:

TIMEGRP RAMS_B = RAMS(N$2);
TIMEGRP RAMPADS = PADS(*);
NET N$32 TNM = RAMS_B;
TIMESPEC TS02 = FROM:RAMS_B:TO:RAMPADS:20;

Then the resulting .pcf file would look like this:

SCHEMATIC START ;
TIMEGRP "RAMS_B" = BEL "N$2" ;
TIMEGRP "RAMPADS" = PADS ("*") ;
TS02 = MAXDELAY FROM TIMEGRP "RAMS_B" TO TIMEGRP "RAMPADS" 20 nS ;
SCHEMATIC END ;

The BEL "N$2" doesn't actually exist, so this TIMEGRP is empty.  To
workaround this problem change the TIMEGRP line in the .pcf file to:

TIMEGRP "RAMS_B" = BEL "BEL_N$2.F" BEL "BEL_N$2.G" ;

Now the TIMEGRP is valid and the constrinat may be used.  One easy way
to find out which are all the RAMs in a design that fit into this
catagory is to do the following:

1. Place th following line in your .ucf file:
TIMEGRP "ALLRAMS" = RAMS ("*") ;

2. Implement the design through MAP and run a verbose TRCE:
trce -v <design_name>

3. Check the trce report file for the BEL names for both the TIMEGRP
to be created and the ALLRAMS TIMEGRP:

Table of Timegroups:
-------------------
TimeGroup RAMS_B:
BELs:
 N$2

TimeGroup ALLRAMS:
BELs:
 N$1	    BEL_N$2.G  BEL_N$2.F

In the above .twr file, N$2 is the obvious match.




End of Record #2443

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents