Answers Database

Configuration: Async Periph mode, RDY/BSY state when DONE is held low


Record #2446

Product Family:  Documentation

Product Line:  FPGA Apps.

Problem Title:
Configuration: Async Periph mode, RDY/BSY state when DONE is held low


Problem Description:
Keywords: Async, peripheral, config, rdy, bsy, done, low, synch

Urgency: Standard

General Description:
When configuring a device through Asynchronous Peripheral mode, is
the RDY/BSY pin still active when the DONE pin is held low to stall
startup and operation?


Solution 1:

The RDY/BSY pin is active until  the I/O's are released.  With the
default makebits or bitgen options, the I/O's are released after
the DONE pin is released.  So if the DONE pin is held low (and
SyncToDone is enabled, see comments below) then the RDY/BSY pin
will still be active.

However, the  RDY/BSY pin will not indicate BSY (BSY = 0) just because
the DONE pin is being help low.  The RDY/BSY pin will only indicate
BSY if the FPGA is serializing the data on the 8 bit data bus for
configuration.	If the DONE is held low, but no data is being written
to the bus, then RDY/BSY will indicate RDY.


SyncToDone:
The holding the DONE pin low can stall startup and operation only
if the SyncToDone option is enabled in makebits or bitgen.  If
SyncToDone is not set then the FPGA will not monitor the external
state of the DONE pin, it will release the DONE pin at the end
of configuration and proceed with startup whether the DONE pin
is externally held low or not.



End of Record #2446