Answers Database

XC4000E, ES-VERILOG library OFDTX simulation model: Z at output generates an X, which propagates to output through feedback path


Record #2464

Product Family:  Software

Product Line:  Cadence

Problem Title:
XC4000E, ES-VERILOG library OFDTX simulation model: Z at output
generates an X, which propagates to output through feedback path



Problem Description:
Keywords: ofd verilog xact es-verilog

Urgency: standard

General Description:

The OFDTX model in the 4000E ES-Verilog library is incorrect.
If CE=0 (hold value) and the output is tristated, the data is
destroyed because the o pin feeds back to the mux that uses CE
to select between the D input and the previous state of the
output.

It should be the q_int signal that gets fed back.


Solution 1:

The needed correction is to replace the "o" in the following
UDP instance's port list with "q_int":

U_MUX_2_1  INST_MUX  (d_int, o, d, ce);
			     ^^
i.e., the correct instantiation is:

U_MUX_2_1  INST_MUX  (d_int, q_int, d, ce);

This problem has already been fixed in the M1 Unified Library for the XC4000E ar
chitecture.



End of Record #2464