Answers Database

M1 QuickHDL: How to compile the HDL simprim, LogiBLOX, and Unisim libraries


Record #2478

Product Family:  Software

Product Line:  Mentor

Problem Title:
M1 QuickHDL: How to compile the HDL simprim, LogiBLOX, and Unisim
libraries



Problem Description:
Keywords: qvhcom, qvlcom, QuickHDL, simulation, simprims, LogiBLOX, Unisims, VHD
L, Verilog, VITAL

Urgency: Hot

General Description:

To perform timing or post-synthesis functional HDL simulation in M1, the
Verilog and/or VHDL (VITAL) simprim models must be compiled for use in
QuickHDL.  If instantiated LogiBLOX and/or Unified library components are
to be behaviorally simulated, the LogiBLOX and/or Unisim libraries must be
compiled, as well.


Solution 1:

M1 includes the following scripts that automatically compile the Verilog
and VHDL simulation models for your particular version of QuickHDL:

   $XILINX/mentor/data/verilog/compile_verilog_libs.sh
   $XILINX/mentor/data/vhdl/compile_vhdl_libs.sh

For more information on using these scripts, see the accompanying README
files.	These scripts should be run by your system administrator.

Note: The Verilog compile script will only compile XC3000, XC4000X (not
XC4000E), and XC5200 Unisim models (M1.4 and later only).  To compile the
Unisim libraries for other device families, see Part 2 of this Solution
Record.



Solution 2:

The information below is intended mainly for reference.  Since compile
scripts for QuickHDL are already included with the Mentor Graphics
interface, you should not need the following instructions unless you need
to compile Unisim libraries for families not listed in the Verilog compile
script (e.g., XC4000E or XC9500), have problems with the compile scripts
or need to perform a partial library compilation.

M1 contains three types of HDL simulation libraries:

   simprim  - Library of generic simulation primitives
   LogiBLOX - Library of LogiBLOX simulation models
   Unisim   - Library of Unified component simulation models (M1.4+)

The instructions that follow reference the following variables:

   VERILOG_DESTN - Location for compiled Verilog libraries
		   Recommended setting: $XILINX/mentor/data/verilog

   VHDL_DESTN	 - Location for compiled VHDL libraries
		   Recommended setting: $XILINX/mentor/data/vhdl

If you want logical library names to be available for all designs, set your
QUICKHDL environment variable to the location of your master quickhdl.ini file,
e.g.:

   setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini

If QUICKHDL is not set when qhmap is run, the logical library mapping is
done locally, and therefore all qhmap commands would have to be run for
each new HDL design.

For Verilog users, the compilation commands that need to be executed are:

   simprim
   -------
   qhlib $VERILOG_DESTN/simprim
   qhmap simprim $VERILOG_DESTN/simprim
   qvlcom -work simprim $XILINX/verilog/data/*.vmd

   LogiBLOX
   --------
   (none required)

   Unisim
   ------
   qhlib $VERILOG_DESTN/uni3000
   qhmap uni3000 $VERILOG_DESTN/uni3000
   qvlcom -work uni3000 $XILINX/verilog/src/UNI3000/*.v

   qhlib $VERILOG_DESTN/uni4000e   # Not included in compile script
   qhmap uni4000e $VERILOG_DESTN/uni4000e
   qvlcom -work uni4000e $XILINX/verilog/src/UNI4000E/*.v

   qhlib $VERILOG_DESTN/uni4000x
   qhmap uni4000x $VERILOG_DESTN/uni4000x
   qvlcom -work uni4000x $XILINX/verilog/src/UNI4000X/*.v

   qhlib $VERILOG_DESTN/uni5200
   qhmap uni5200 $VERILOG_DESTN/uni5200
   qvlcom -work uni5200 $XILINX/verilog/src/UNI5200/*.v

   qhlib $VERILOG_DESTN/uni9000    # Not included in compile script
   qhmap uni9000 $VERILOG_DESTN/uni9000
   qvlcom -work uni9000 $XILINX/verilog/src/UNI9000/*.v

For VHDL users, the commands are:

   simprim
   -------
   qhlib $VHDL_DESTN/simprim
   qhmap simprim $VHDL_DESTN/simprim
   qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
   qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vcompoents.vhd
   qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd

   LogiBLOX
   --------
   qhlib $VHDL_DESTN/logiblox
   qhmap logiblox $VHDL_DESTN/logiblox
   qvhcom -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
   qvhcom -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
   qvhcom -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd

   Unisim
   ------
   qhlib $VHDL_DESTN/unisim
   qhmap unisim $VHDL_DESTN/unisim
   qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
   qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
   qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
   qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

   qhlib $VHDL_DESTN/unisim_5k
   qhmap unisim_5k $VHDL_DESTN/unisim_5k
   qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
   qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
   qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
   qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
   qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd



End of Record #2478