Answers Database

VERILOG, SYNOPSYS: How to constrain I/O pins in Verilog designs (I/O pin locking)


Record #2500

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG, SYNOPSYS:  How to constrain I/O pins in Verilog designs (I/O
pin locking)



Problem Description:
Keywords: pin location lock constrain verilog

Urgency: standard

General Description:
The question often arises as to how you can constrain your
I/O to specific pad locations in a synthesis flow when your
design entry format is Verilog.

There is actually no support for adding attributes directly
to components in a Verilog netlist, however, I/O location constraints can be add
ed using one of the following techniques
instead:

 - adding constraints to a .cst file (for XACT)
 - adding constraints to a .ucf file (for M1) constraint



Solution 1:


If you are using Synopsys, you may use the command:

  set_attribute <port_name> "pad_location" -type string "<pin_number>"

This is detailed in the XSI User/Interface guide, pg5-15.
You may also use a .cst file (for XACT)
  or a .ucf file (for M1) constraint instead.




Solution 2:

There is actually no support for adding attributes directly
to components in a Verilog netlist, however, I/O location constraints can be add
ed using one of the following techniques
instead:

 - adding constraints to a .cst file (for XACT)
 - adding constraints to a .ucf file (for M1) constraint




End of Record #2500