Answers Database

NGD2VER M1.2/M1.3/M1.4: ERROR (245) Verilog file parsing failed / Erroron or before token ',' /Escaped names (names prefixed with "\") in Verilog netli sts generated by NGD2VER


Record #2533

Product Family:  Software

Product Line:  Merged Core

Problem Title:
NGD2VER M1.2/M1.3/M1.4:	ERROR (245) Verilog file parsing failed /
Erroron or before token ',' /Escaped names (names prefixed with "\") in Verilog
netli
sts generated by NGD2VER



Problem Description:
Keywords: escape Verilog illegal character "\"

Urgency: hot

General Description:

The backslash is used as an escape character in Verilog.
In the M1 release, NGD2VER "escapes" any net or block name
containing Verilog-illegal characters.	An escaped Verilog
name can be recognized by:

1. A backslash ("\") prefix in front of that name,
and
2. A terminating blank space.

Example:

      The original net name "p1$i40/empty"  becomes
"\p1$i40/empty " (note the terminating blank space)

because of the Verilog illegal character "/" used as a
hierarchy designator in the input design.

The Verilog-legal set of characters is limited to the
following:

       a-Z, A-Z, 0-9, _, $   (see Xilinx solution 1535)

Commonly encountered Verilog-illegal characters include:

 - period characters ("."'s).	"."'s are reserved characters
   used as hierarchy separators in Verilog.  There are also
   period characters that may be generated by the
   M1 core tools in the process of gating local
   and global RESETs and tristates together.  This is mainly
   an issue in the M1.2.11 release.  In the M1.3
   version of NGD2VER, these core-tool generated "."'s
   are now converted into  "_"	characters.

 - "/"'s, which are usually used as hierarchical delimiters.

NGD2VER will also escape any reserved Verilog names that are
used in a design (e.g., "input", "output", etc.).

By rights, Verilog-XL and any OVI/IEEE 1364-compliant
simulator *should* accept escaped Verilog names. Currently
there is a known problem with escaped character
names in the Veritools "Undertow" waveform analyzer where
these cause incorrect simulation results (outputs stuck at X).
IKOS has problems handling these names when they are used
as part of the name of a .pin file (the terminating blank
space character is omitted from the .pin file name).

There are no known problems with the current Cadence release
(97A) of Verilog-XL and the new Simwaves waveform viewer.


Solution 1:

In those cases where the name is escaped only because of
forward slashes ("/") used as hierarchy separators in the
original name reprocessing the .NGA (or .NGD) file through
NGD2VER with an additional "-u" option will solve the
problem by replacing the "/" characters with "_" characters.



Solution 2:

If you do not want escaped Verilog names in your
netlist, you can write a script to replace the "\"'s, the
terminating blank spaces, and all other Verilog-illegal
characters with "_" (underscore) symbols.




End of Record #2533