Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


bitgen: WARNING:x4kdr - netcheck: no load pins found on signal


Record #2544

Problem Title:
bitgen: WARNING:x4kdr - netcheck: no load pins found on signal


Problem Description:
Keywords: bitgen, DRC

Urgency: Standard

General Description:

What is the meaning of bitgen "netcheck: no loads pins
found on signal"?


Solution 1:

These are not bitgen errors, they are drc errors. They are
detected during bitgen because bitgen runs drc by default.
They are fatal to bitgen, but not to other applications.

You can avoid them by using the -d switch to disable DRC
during bitgen, but it would be better to investigate why the
DRC problems exist.

To investigate, run DRC on the .ncd file (from EPIC or from
command line) at various stages to determine when the drc
errors were introduced. If they exist on the mapped design,
investigate it as a MAP issue.	If the errors don't appear
until after PAR, it is a PAR issue.

Possible causes:

If the .ncd output by map exhibits the problem and map was run
with the "-u" switch, then the problem is likely a design
error.

If the .ncd output by map exhibits the problem and map was not
run with the "-u" switch, then the problem is likely a map
bug due to corrupted logic.

If the mapped .ncd is okay, but the output of par exhibits the
problem, the problem is likely a par bug, usually due to pin
swapping.

Was the design modified in EPIC? If so, it could be user
error.	Check if the net is part of a hard macro that's not
connected properly.

If the input design has nets with no loads, they would
normally be clipped during map. Check for S attributes or for
the No Clip property that prevent this clipping.

This is not just a case of unrouted nets. It is a case of
loadless nets which causes the DRC errors. These are usually
mapping/user errors. They are occasionally caused due to pin
swapping bugs in par.



End of Record #2544

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents