Answers Database

M1: Board-level schematic simulation methodology for QuickSim


Record #2560

Product Family:  Software

Product Line:  Mentor

Problem Title:
M1: Board-level schematic simulation methodology for QuickSim


Problem Description:
Keywords: board-level, simulation, QuickSim, viewpoint, DVE

Urgency: hot

General Description:

Simulating board-level designs requires some knowledge of viewpoint
management in Mentor Graphics.	Two simulation viewpoints are created, one
for functional simulation and one for timing simulation.  Each Xilinx
component is then linked into the two simulation viewpoints.  With M1, all
schematic designs are linked to the board-level design in the same manner,
regardless of whether these designs contain LogiBLOX modules or not.

This application brief discusses the creation and management of simulation
viewpoints, as well as the importation of Xilinx-level functional and
timing information into board-level viewpoints.


Solution 1:

FILES YOU WILL NEED FOR XILINX BOARD-LEVEL SIMULATION

Download the following archive from the Xilinx Download Area:

   ftp://ftp.xilinx.com/pub/swhelp/mentor/boardmen_m1.tar.Z

This archive contains the following scripts:

   xbvpt
   regmodel
   unregmodel
   getreg.nawk

A README file is also included.

XBVPT (Xilinx Board-Level Viewpoint) generates or annotates a functional or
timing board-level design viewpoint with information required by Xilinx
simulation models.  The REGMODEL script (along with the GETREG subscript)
register the simulation models for each Xilinx-level portion of the design.
The last utility, UNREGMODEL, lets you quickly unregister schematic or EDDM
models in case of misregistration.  All of these scripts should be placed
in a directory specified in your PATH variable.



Solution 2:

GENERATING BOARD-LEVEL FUNCTIONAL AND TIMING VIEWPOINTS

In this example, assume you have the following board-level schematic:

   $CARD_XYZ/boardeaux

The following viewpoints are generated:

   $CARD_XYZ/boardeaux/functional
		       timing

The XBVPT script simplifies viewpoint generation.  For usage information on
this script, type "xbvpt" by itself on the command line.

1. To create a functional viewpoint, type the following command:

      xbvpt -f $CARD_XYZ/boardeaux

   This creates the viewpoint $CARD_XYZ/boardeaux/functional.  Note
   that "-f" is optional; XBVPT defaults to creating a functional
   viewpoint.  Also note that the component name can be a hard name or
   soft name.

   This script writes Xilinx-specific properties into the board-level
   viewpoint.  In addition, it includes the following setting:

      $add_parameter("xilinx_simtype", "functional", @string);

   The xilinx_simtype parameter allows Xilinx components to be changed
   easily between functional and timing models in QuickSim by simply
   changing which viewpoint is fed into the simulator.

   NOTE: If you have already created a board-level functional simulation
   viewpoint for your design (e.g., my_functional_viewpoint), use the
   following command to annotate information into your viewpoint:

      xbvpt -f $CARD_XYZ/boardeaux my_functional_viewpoint

2. To create a timing viewpoint, type the following command:

      xbvpt -f $CARD_XYZ/boardeaux

   This creates the viewpoint $CARD_XYZ/boardeaux/timing.

   This script writes Xilinx-specific properties into the board-level
   viewpoint, including this $add_parameter setting similar to the one used
   for the functional viewpoint:

      $add_parameter("xilinx_simtype", "timing", @string);

   NOTE: If you have already created a board-level timing simulation
   viewpoint for your design (e.g., my_timing_viewpoint), use the
   following command to annotate information into your viewpoint:

      xbvpt -t $CARD_XYZ/boardeaux my_timing_viewpoint

3. Follow the instructions in the next section to import each Xilinx
   component into the board-level viewpoints for simulation.

4. To run a particular simulation on the design, specify the VIEWPOINT name
   on the QuickSim command line, rather than just the component name.  For
   example, to run a functional simulation:

      pld_quicksim boardeaux/functional -tim unit

   To run a timing simulation:

      pld_quicksim boardeaux/timing -tim typ -cp

Note the cross-probing switch at the end of the timing command.  When using
cross-probing, load the FUNCTIONAL viewpoint boardeaux/functional into DVE;
this allows you to annotate back-end timing results onto your front-end
schematic.

As explained in the next section, the correct Xilinx models (for functional
or timing simulation) are automatically pulled into QuickSim based on the
value of the xilinx_simtype parameter.

Note: There is currently no way to independently reset Xilinx components in
Quicksim.  All XC2000 and XC3000 devices must share a common //globalresetb
signal, all XC4000 devices must share a common //globalsetreset signal, all
XC5200 devices must share a common //globalreset signal, and all XC7000
devices most share a common //prld signal.



Solution 3:

IMPORTING A SCHEMATIC DESIGN INTO THE BOARD-LEVEL SIMULATION MODEL

Assume you have the following Xilinx component:

   $CARD_XYZ/xilinx/ifctl: XC4000E design
      (instance name: BRIDGE)

1. Attach these properties to the FPGA instance in the boardeaux schematic:

      NAME	       VALUE		TYPE
      lca_technology   xc4000e		string
      MODEL	       xilinx_simtype	expression

   (These may also be made body properties on the symbols themselves.)

   Note the MODEL property, which is used to swap between functional and
   timing models.  Setting this property to be of type EXPRESSION (instead
   of STRING) allows this property to be changed dynamically, as seen by
   QuickSim, by simply telling the simulator which viewpoint to use.

TO PREPARE FOR FUNCTIONAL SIMULATION

2. Use the Component Interface Browser to add a "functional" label to the
   original schematic model.  You can do this using the REGEDDM script:

      regmodel -f ifctl ifctrl/schematic

   (You may leave off the "/schematic" if you wish.)

   After you run REGMODEL, you can look at the cib_view.log file and see a
   listing structured like the following:

      ** view
	 COMPONENT  ifctl	   DEFAULT INTERFACE IS:  ifctl

	    INTERFACE:	ifctl
	       PINS:
		  (list of pins)
	       BODY PROPERTIES:  (list)
	       INTERFACE MODEL ENTRIES:
	       Model Entry     Type	Model Info
		  (list)

   Note that there may be more than one INTERFACE line, the interface we
   care about is the one named in the DEFAULT INTERFACE field.

   At the bottom of the interface description, you will see the following:

      0 mgc_symbol     Path: $CARD_XYZ/xilinx/ifctl/ifctl
		       Labels: 'default_sym'
		       Status: Valid for interface; Valid for property

      1 mgc_schematic  Path: $CARD_XYZ/xilinx/ifctl/schematic
		       Labels: '$schematic' 'schematic' 'default' 'functional'
		       Status: NOT valid for interface; NOT valid for property

   REGMODEL has added a "functional" label to the original schematic model.

   The model we have labeled will be accessible by any instantiation of
   this instance which has a MODEL=functional property attached to it.
   When you tell QuickSim to run on the functional viewpoint, the parameter
   xilinx_simtype=functional changes the MODEL=xilinx_simtype(exp) to
   become MODEL=functional as seen by QuickSim.  QuickSim then pulls in the
   original schematic, which now has a label of "functional".

You are now ready to run QuickSim for functional simulation.

TO PREPARE FOR TIMING SIMULATION

Step 3 (and only Step 3) will need to be rerun on the FPGA design whenever
this part of the design is modified.

3. After the design has been implemented by the FPGA tools, run ngd2edif,
   and pld_edif2tim to generate a Mentor EDDM model:

      ngd2edif -w -v mentor ifctl.nga ifctl.edn
      pld_edif2tim -r ifctl.edn

   To set the vendor switch ("-v mentor") in the Xilinx Design Manager/Flow
   Engine, go to the Implementation Options Template.  Under the Interface
   panel, change the Simulation Data Options: Vendor setting to "Mentor".

   This generates a $CARD_XYZ/xilinx/ifctl_lib/ifctl EDDM single-object
   netlist with timing information.

4. Register the EDDM model with the original component in CIB as before,
   but instead of using the -f option in REGMODEL, use the -t option:

      regmodel -t ifctl ifctl_lib/ifctl/view_1

   (You may leave off the "/view_1" if you wish.)

   The cib_view.log file will now show:

      2 Eddm_single_object  Path: $CARD_XYZ/xilinx/ifctl_lib/ifctl/view_1
		       Labels: '$schematic' 'schematic' 'timing'
		       Status: NOT valid for interface; NOT valid for property

   The model you have registered will be accessible by any instantiation of
   this instance which has a MODEL=timing property attached to it.  When
   you tell QuickSim to run on the timing viewpoint, the parameter
   xilinx_simtype=timing changes the MODEL=xilinx_simtype(exp) to become
   MODEL=timing as seen by QuickSim.  QuickSim then pulls in the newly
   registered model whose label is "timing", which is how you labeled the
   model that Timsim8 generated.

You are now ready to run QuickSim for timing simulation.



End of Record #2560