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VERILOG-XL / ES-VERILOG v 5.2.1: Warning! Delay value is negative or too large: set to 0 [Verilog-SVTL] "/products/esv522/verilog4000e"


Record #2561

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL / ES-VERILOG v 5.2.1:  Warning!  Delay value is negative or
too large: set to 0    [Verilog-SVTL]	     "/products/esv522/verilog4000e"



Problem Description:
Keywords: negative verilog synchronous dual port ram,
timenetx, funcnetx, ES-VERILOG 5.2.1

Urgency: standard

General Description:

Warnings of the form:

  Warning!  Delay value is negative or too large: set to 0
  [Verilog-SVTL]

	  "/tools/esv521/verilog4000e/
	  ram32x1s.v", 99: -1

may be issued on 4000E designs containing synchronous or
dual port RAM when simulating with ES-Verilog.

Modeling of the synchronous and dual port RAMs in this
interface requires the use of negative delay values.
However, by default, Verilog-XL does not accept negative
delays and issues the warning above.


Solution 1:


To make Verilog-XL accept the negative delay values as well
as support the split setup and hold time method used in the
SDF modeling of these RAMs, you must invoke
Verilog using two additional, nondefault options:

    +neg_tchk and +splitsuh



Example:  verilog +neg_tchk +splitsuh design.v testbench.v




End of Record #2561