Answers Database

M1, NGD2VER: How to retain design hierarchy in a Verilog simulation netlist generated by NGD2VER


Record #2573

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1, NGD2VER: How to retain design hierarchy in a Verilog simulation
netlist generated by NGD2VER



Problem Description:
Keywords: ngd2ver, hierarchy

Ugency: Standard

netlist program, NGD2VER is a flattened structural netlist by
default.

How can I retain the hierarchy of my original design when
running NGD2VER?


Solution 1:


Note: This option has been added to the new Simulation template
within Design Manager for the Alliance 1.5 release.  If you are
using A1.5 Design Manager, the following instructions do not apply
and the retain hierchy switch should be set from the Simulation
Template.

There is a switch which you can use to specify the generation
of a hierarchical Verilog netlist for simulation.  The -r
switch will create a Verilog netlist consisting of multiple
Verilog modules so that the design hierarchy may be maintained for simulation pu
rposes.

To use this switch:

From command line:

   ngd2ver -r <other desired switches> <design.ngd or
   design.nga>

From the Design Manager:

This switch must be added to the custom menu of the Template
Manager in the following manner:

  Program Name: ngd2ver
  Program Options: -r

For more information on using the Template Manager, please
refer to (Xilinx Solution 1227).



End of Record #2573