Answers Database
EZtag: "Input passed end of file" message when programming 9572 CPLD
Record #2575
Product Family: Software
Product Line: EPLD Core
Problem Title:
EZtag: "Input passed end of file" message when programming 9572 CPLD
Problem Description:
Keywords: 9572, eztag, eof, end of file
Urgency: standard
General Description:
The fitter seems to complete successfully but when the the
<design>.jed file is loaded into EZTAG a message appears saying
that the Input is passed end of file.
Solution 1:
On examination, the user will most likely find that the file
length of the <design>.jed file is zero. This is because the
9572 was not supported with the early versions of XACT-CPLD and
XABEL-CPLD. The fitter reports that the device is not
supported in the fe.log file and a 0 length JED file is
created.
To upgrade to a later version of the software that supports the
9572, getget following two update patches from the Xilinx web
or ftp site:
For a PC :
ftp://ftp.xilinx.com/pub/swhelp/cpld/eztag_pc.zip
ftp://ftp.xilinx.com/pub/swhelp/cpld/fitterpc.zip
For a Sun workstation :
ftp://ftp.xilinx.com/pub/swhelp/cpld/eztag_sn.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/cpld/fittersn.tar.Z
For a HP workstation :
ftp://ftp.xilinx.com/pub/swhelp/cpld/eztag_hp.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/cpld/fitterhp.tar.Z
For further information about these patches please look at the
file called cpld.lst located :
ftp://ftp.xilinx.com/pub/swhelp/cpld/cpld.lst
which will indicate the last changes made to these files.
End of Record #2575
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |