Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


9500: How to utilize the wired-AND in the UIM


Record #2579

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
9500: How to utilize the wired-AND in the UIM


Problem Description:
Keywords: wired, and, UIM, wand, fitter, hitop

Urgency: standard

General Description: How can a user utilize the Wired-AND
capibilities in the UIM of the 9500.


Solution 1:

XACT:

By default, the 9500 fitter software will attempt to
automatically utilize this feature if it is possible.
However, if a designer wants to force this to occur,
this can be done by attaching the following attribute
on the desired AND gate:

OPT=UIM

Note: the wired-AND feature is implemented in the UIM.
Thus, the inputs to the desired AND gate must come
from feedback loops.  Thus, if any of the AND gate inputs
are from inputs pins, the UIM wired-AND can not be used
to implement the AND gate.

Also, a wired-AND function can be implemented in the UIM only
for a single level of logic.

For example, if your equation looks like y = a*b*c, it can be
implemented as a wired-AND. However, if your function looks
like z = c*d + e*f, then you can implement the function z as
one wired-AND gate. You will need two AND gates to implement
that.



Solution 2:

A1/F1

The same details are true for M1 except for the syntax placed
on the logic on the schematic.

WIREAND

is the attribute added to an AND gate to force HITOP to place
the gate in the UIM.

To place this attribute in a UCF file:

NET signal_name WIREAND;

where signal_name is the output signal of the AND gate.



End of Record #2579

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents