Answers Database

Foundation XVHDL F1.3/F1.4: VHDL compiler synthesizes design twice


Record #2606

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL F1.3/F1.4:  VHDL compiler synthesizes design twice


Problem Description:
Keywords:  XVHDL, Logiblox

Urgency:  Standard

General Description:

The XVHDL compiler will run the synthesis of the design twice
if Logiblox are inferred.


Solution 1:

If Logiblox modules are inferred by the XVHDL compiler, the
synthesis compiler will run twice -- once to generate a .EDN
EDIF file for implementation, and once to generate a .EDF EDIF
file, without Logiblox, for functional simulation.

The only way to force it to compile just once is to disable the
Logiblox inference by deselecting the Logiblox option in the
Synthesis -> Options dialog of the HDL Editor.

Logiblox inference may be disabled when doing multiple
iterations of functional simulation, to reduce runtime of the
synthesizer.  However, it is recommended that when going into
the Design Implementation portion of the flow, the Logiblox
inference switch is enabled to provide optimal results and
performance in the design.



End of Record #2606