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M1 CONCEPT/CONCEPT2XIL: generating a symbol body for a non-schematic block, using a Verilog .v file as input


Record #2644

Product Family:  Software

Product Line:  Cadence

Problem Title:
M1 CONCEPT/CONCEPT2XIL: generating a symbol body for a non-schematic
block, using a Verilog .v file as input



Problem Description:
Keywords: concept symbol body board

Urgency: standard

General Description:
Often it is necessary to generate a symbol body from a
non-schematic block in order to integrate the block
into a Concept schematic.  This solution describes the
procedure for generating the Concept body for such a block
using the M1 Cadence Concept interface and a Verilog
description of the subblock's ports, as might be generated
by LogiBLOX or CoreGEN.


Solution 1:

The M1 Concept interface compiles an EDIF netlist for a
Concept schematic by first going through a Verilog netlist
intermediate.  For this reason, any non-schematic subblocks
(XNF, NGO, EDIF, etc.) which must be integrated into a Concept
schematic must at minimum also have a Verilog netlist
containing at least a port list for the subblock.

Example:  The following is an example of a minimal
Verilog netlist for an 8x8 multiplier subblock:

  module m8x8 (
	a,
	b,
	prod,
	c);

    input [7:0] a;
    input [7:0] b;
    output [15:0] prod;
    input c;

  endmodule

To generate a body for a design subblock which is
in the form of a Verilog netlist (as for a
LogiBLOX module), follow these instructions:


1. Copy the .v file to your project directory.

NOTE! Make sure that the name of the .v file for the subblock
is the SAME as the name of Verilog module record in the .v
file describing this subblock.

2. Start up Concept.

3. From the command line within Concept (at the bottom of
the schematic window), type:

  genview -i block_name.v -v logic body verilog

  When invoked with these options, GENVIEW will:

  a. Generate a directory called "block_name"
     for this block in your project directory.

  b. Generate a symbol body file,
     body.1.1, for the block in this directory.

  c. Create a subdirectory called "logic" within
     this block_name directory, and copy the
     "block_name.v" file to this logic subdirectory, renaming
     it as "verilog.v".

  d. Update your <design>.wrk library
     file, adding a new entry referencing the new component.

4. Next navigate to the directory:

    block_name/logic

5. Open the verilog.v file in a text editor and add the
following line after the beginning of the module declaration
for this block:

  parameter cds_action="ignore";

This parameter is a flag to the CONCEPT2XIL netlister
that tells it that there are no additional levels of
hierarchy (subblocks) underlying this non-schematic module.

Example:

   module mycount (load, up_dn, clk_en, clock, asnc_ctrl,
    term_cnt, d_in, q_out);

   parameter cds_action="ignore";

   input load;
   input up_dn;
   input_clk_en;

   ...

6. Copy the .NGO, XNF, or EDIF file for your subbblock to the
run directory so that it can be merged with the rest of the
design when NGDBUILD is run.

7. Finally, instantiate the symbol in your Concept schematic,
save the schematic, and run CONCEPT2XIL to netlist out the
design.









End of Record #2644