Answers Database

VERILOG-XL: How to specify the SDF file to the Verilog-XL simulator as acommand line option


Record #2650

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL: How to specify the SDF file to the Verilog-XL simulator as
acommand line option



Problem Description:
Keywords:  sdf, command line, verilog-xl

Urgency: standard

General Description:
The SDF delay annotation file can be specified from within
the Verilog simulation netlist, or as a command line option.


Solution 1:

To specify the SDF file as a command line option, use
the +sdf_file option in conjunction with the name of the file:

Example:

  verilog +sdf_file  design1.sdf design1.v design1.stim

This option is documented in the Cadence SDF Annotator User
Guide, p.4-2.



End of Record #2650