Answers Database

M1 CPLD: Synopsys SCAN tutorial test bench does not initialize registers.


Record #2655

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1 CPLD: Synopsys SCAN tutorial test bench does not initialize
registers.



Problem Description:
Keywords: scan, tutorial, simulation

Urgency: standard

General Description:

The test bench in the CPLD synopsys tutorial
($XILINX/synopsys/tutorial/cpld/vhdl/scan_tb.vhd or
$XILINX/synopsys/tutorial/cpld/verilog/scan_tb.v) does not
initialize registers causing bad simulation output.


Solution 1:

Edit the test bench to insert a positive pulse on the CLEAR
input before the first clock pulse.



End of Record #2655